1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Cirrus Logic EP93xx PLL support. 4 * 5 * Copyright (C) 2009 Matthias Kaehlcke <matthias (at) kaehlcke.net> 6 */ 7 8 #include <common.h> 9 #include <asm/arch/ep93xx.h> 10 #include <asm/io.h> 11 #include <div64.h> 12 13 /* 14 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. 15 * 16 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of 17 * the specified bus in HZ. 18 */ 19 20 /* 21 * return the PLL output frequency 22 * 23 * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1) 24 * / (X2IPD + 1) / 2^PS 25 */ 26 static ulong get_PLLCLK(uint32_t *pllreg) 27 { 28 uint8_t i; 29 const uint32_t clkset = readl(pllreg); 30 uint64_t rate = CONFIG_SYS_CLK_FREQ; 31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; 32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; 33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ 34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) 35 rate >>= 1; 36 37 return (ulong)rate; 38 } 39 40 /* return FCLK frequency */ 41 ulong get_FCLK(void) 42 { 43 const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; 44 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; 45 46 const uint32_t clkset1 = readl(&syscon->clkset1); 47 const uint8_t fclk_div = 48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; 49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; 50 51 return fclk_rate; 52 } 53 54 /* return HCLK frequency */ 55 ulong get_HCLK(void) 56 { 57 const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; 58 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; 59 60 const uint32_t clkset1 = readl(&syscon->clkset1); 61 const uint8_t hclk_div = 62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; 63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; 64 65 return hclk_rate; 66 } 67 68 /* return PCLK frequency */ 69 ulong get_PCLK(void) 70 { 71 const uint8_t pclk_divisors[] = { 1, 2, 4, 8 }; 72 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; 73 74 const uint32_t clkset1 = readl(&syscon->clkset1); 75 const uint8_t pclk_div = 76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; 77 const ulong pclk_rate = get_HCLK() / pclk_div; 78 79 return pclk_rate; 80 } 81 82 /* return UCLK frequency */ 83 ulong get_UCLK(void) 84 { 85 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; 86 ulong uclk_rate; 87 88 const uint32_t value = readl(&syscon->pwrcnt); 89 if (value & SYSCON_PWRCNT_UART_BAUD) 90 uclk_rate = CONFIG_SYS_CLK_FREQ; 91 else 92 uclk_rate = CONFIG_SYS_CLK_FREQ / 2; 93 94 return uclk_rate; 95 } 96
