1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * relocate - i.MX27-specific vector relocation 4 * 5 * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot (at) aribaud.net> 6 */ 7 8 #include <asm-offsets.h> 9 #include <config.h> 10 #include <linux/linkage.h> 11 12 /* 13 * The i.MX27 SoC is very specific with respect to exceptions: it 14 * does not provide RAM at the high vectors address (0xFFFF0000), 15 * thus only the low address (0x00000000) is useable; but that is 16 * in ROM. Therefore, vectors cannot be changed at all. 17 * 18 * However, these ROM-based vectors actually just perform indirect 19 * calls through pointers located in RAM at SoC-specific addresses, 20 * as follows: 21 * 22 * Offset Exception Use by ROM code 23 * 0x00000000 reset indirect branch to [0x00000014] 24 * 0x00000004 undefined instruction indirect branch to [0xfffffef0] 25 * 0x00000008 software interrupt indirect branch to [0xfffffef4] 26 * 0x0000000c prefetch abort indirect branch to [0xfffffef8] 27 * 0x00000010 data abort indirect branch to [0xfffffefc] 28 * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000 29 * 0x00000018 IRQ indirect branch to [0xffffff00] 30 * 0x0000001c FIQ indirect branch to [0xffffff04] 31 * 32 * In order to initialize exceptions on i.MX27, we must copy U-Boot's 33 * indirect (not exception!) vector table into 0xfffffef0..0xffffff04 34 * taking care not to copy vectors number 5 (reserved exception). 35 */ 36 37 .section .text.relocate_vectors,"ax",%progbits 38 39 ENTRY(relocate_vectors) 40 41 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ 42 ldr r1, =32 /* size of vector table */ 43 add r0, r0, r1 /* skip to indirect table */ 44 ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */ 45 ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */ 46 stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */ 47 48 bx lr 49 50 ENDPROC(relocate_vectors) 51
