1 config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select ARM_ERRATA_855873 5 select FSL_LSCH2 6 select SYS_FSL_SRDS_1 7 select SYS_HAS_SERDES 8 select SYS_FSL_DDR_BE 9 select SYS_FSL_MMDC 10 select SYS_FSL_ERRATUM_A010315 11 select SYS_FSL_ERRATUM_A009798 12 select SYS_FSL_ERRATUM_A008997 13 select SYS_FSL_ERRATUM_A009007 14 select SYS_FSL_ERRATUM_A009008 15 select ARCH_EARLY_INIT_R 16 select BOARD_EARLY_INIT_F 17 select SYS_I2C_MXC 18 select SYS_I2C_MXC_I2C1 19 select SYS_I2C_MXC_I2C2 20 imply PANIC_HANG 21 22 config ARCH_LS1043A 23 bool 24 select ARMV8_SET_SMPEN 25 select ARM_ERRATA_855873 26 select FSL_LSCH2 27 select SYS_FSL_SRDS_1 28 select SYS_HAS_SERDES 29 select SYS_FSL_DDR 30 select SYS_FSL_DDR_BE 31 select SYS_FSL_DDR_VER_50 32 select SYS_FSL_ERRATUM_A008850 33 select SYS_FSL_ERRATUM_A008997 34 select SYS_FSL_ERRATUM_A009007 35 select SYS_FSL_ERRATUM_A009008 36 select SYS_FSL_ERRATUM_A009660 37 select SYS_FSL_ERRATUM_A009663 38 select SYS_FSL_ERRATUM_A009798 39 select SYS_FSL_ERRATUM_A009929 40 select SYS_FSL_ERRATUM_A009942 41 select SYS_FSL_ERRATUM_A010315 42 select SYS_FSL_ERRATUM_A010539 43 select SYS_FSL_HAS_DDR3 44 select SYS_FSL_HAS_DDR4 45 select ARCH_EARLY_INIT_R 46 select BOARD_EARLY_INIT_F 47 select SYS_I2C_MXC 48 select SYS_I2C_MXC_I2C1 49 select SYS_I2C_MXC_I2C2 50 select SYS_I2C_MXC_I2C3 51 select SYS_I2C_MXC_I2C4 52 imply SCSI 53 imply SCSI_AHCI 54 imply CMD_PCI 55 56 config ARCH_LS1046A 57 bool 58 select ARMV8_SET_SMPEN 59 select FSL_LSCH2 60 select SYS_FSL_SRDS_1 61 select SYS_HAS_SERDES 62 select SYS_FSL_DDR 63 select SYS_FSL_DDR_BE 64 select SYS_FSL_DDR_VER_50 65 select SYS_FSL_ERRATUM_A008336 66 select SYS_FSL_ERRATUM_A008511 67 select SYS_FSL_ERRATUM_A008850 68 select SYS_FSL_ERRATUM_A008997 69 select SYS_FSL_ERRATUM_A009007 70 select SYS_FSL_ERRATUM_A009008 71 select SYS_FSL_ERRATUM_A009798 72 select SYS_FSL_ERRATUM_A009801 73 select SYS_FSL_ERRATUM_A009803 74 select SYS_FSL_ERRATUM_A009942 75 select SYS_FSL_ERRATUM_A010165 76 select SYS_FSL_ERRATUM_A010539 77 select SYS_FSL_HAS_DDR4 78 select SYS_FSL_SRDS_2 79 select ARCH_EARLY_INIT_R 80 select BOARD_EARLY_INIT_F 81 select SYS_I2C_MXC 82 select SYS_I2C_MXC_I2C1 83 select SYS_I2C_MXC_I2C2 84 select SYS_I2C_MXC_I2C3 85 select SYS_I2C_MXC_I2C4 86 imply SCSI 87 imply SCSI_AHCI 88 89 config ARCH_LS1088A 90 bool 91 select ARMV8_SET_SMPEN 92 select ARM_ERRATA_855873 93 select FSL_LSCH3 94 select SYS_FSL_SRDS_1 95 select SYS_HAS_SERDES 96 select SYS_FSL_DDR 97 select SYS_FSL_DDR_LE 98 select SYS_FSL_DDR_VER_50 99 select SYS_FSL_EC1 100 select SYS_FSL_EC2 101 select SYS_FSL_ERRATUM_A009803 102 select SYS_FSL_ERRATUM_A009942 103 select SYS_FSL_ERRATUM_A010165 104 select SYS_FSL_ERRATUM_A008511 105 select SYS_FSL_ERRATUM_A008850 106 select SYS_FSL_ERRATUM_A009007 107 select SYS_FSL_HAS_CCI400 108 select SYS_FSL_HAS_DDR4 109 select SYS_FSL_HAS_RGMII 110 select SYS_FSL_HAS_SEC 111 select SYS_FSL_SEC_COMPAT_5 112 select SYS_FSL_SEC_LE 113 select SYS_FSL_SRDS_1 114 select SYS_FSL_SRDS_2 115 select FSL_TZASC_1 116 select ARCH_EARLY_INIT_R 117 select BOARD_EARLY_INIT_F 118 select SYS_I2C_MXC 119 select SYS_I2C_MXC_I2C1 120 select SYS_I2C_MXC_I2C2 121 select SYS_I2C_MXC_I2C3 122 select SYS_I2C_MXC_I2C4 123 imply SCSI 124 imply PANIC_HANG 125 126 config ARCH_LS2080A 127 bool 128 select ARMV8_SET_SMPEN 129 select ARM_ERRATA_826974 130 select ARM_ERRATA_828024 131 select ARM_ERRATA_829520 132 select ARM_ERRATA_833471 133 select FSL_LSCH3 134 select SYS_FSL_SRDS_1 135 select SYS_HAS_SERDES 136 select SYS_FSL_DDR 137 select SYS_FSL_DDR_LE 138 select SYS_FSL_DDR_VER_50 139 select SYS_FSL_HAS_CCN504 140 select SYS_FSL_HAS_DP_DDR 141 select SYS_FSL_HAS_SEC 142 select SYS_FSL_HAS_DDR4 143 select SYS_FSL_SEC_COMPAT_5 144 select SYS_FSL_SEC_LE 145 select SYS_FSL_SRDS_2 146 select FSL_TZASC_1 147 select FSL_TZASC_2 148 select SYS_FSL_ERRATUM_A008336 149 select SYS_FSL_ERRATUM_A008511 150 select SYS_FSL_ERRATUM_A008514 151 select SYS_FSL_ERRATUM_A008585 152 select SYS_FSL_ERRATUM_A008997 153 select SYS_FSL_ERRATUM_A009007 154 select SYS_FSL_ERRATUM_A009008 155 select SYS_FSL_ERRATUM_A009635 156 select SYS_FSL_ERRATUM_A009663 157 select SYS_FSL_ERRATUM_A009798 158 select SYS_FSL_ERRATUM_A009801 159 select SYS_FSL_ERRATUM_A009803 160 select SYS_FSL_ERRATUM_A009942 161 select SYS_FSL_ERRATUM_A010165 162 select SYS_FSL_ERRATUM_A009203 163 select ARCH_EARLY_INIT_R 164 select BOARD_EARLY_INIT_F 165 select SYS_I2C_MXC 166 select SYS_I2C_MXC_I2C1 167 select SYS_I2C_MXC_I2C2 168 select SYS_I2C_MXC_I2C3 169 select SYS_I2C_MXC_I2C4 170 imply DISTRO_DEFAULTS 171 imply PANIC_HANG 172 173 config FSL_LSCH2 174 bool 175 select SYS_FSL_HAS_CCI400 176 select SYS_FSL_HAS_SEC 177 select SYS_FSL_SEC_COMPAT_5 178 select SYS_FSL_SEC_BE 179 180 config FSL_LSCH3 181 bool 182 183 config FSL_MC_ENET 184 bool "Management Complex network" 185 depends on ARCH_LS2080A || ARCH_LS1088A 186 default y 187 select RESV_RAM 188 help 189 Enable Management Complex (MC) network 190 191 menu "Layerscape architecture" 192 depends on FSL_LSCH2 || FSL_LSCH3 193 194 config FSL_PCIE_COMPAT 195 string "PCIe compatible of Kernel DT" 196 depends on PCIE_LAYERSCAPE 197 default "fsl,ls1012a-pcie" if ARCH_LS1012A 198 default "fsl,ls1043a-pcie" if ARCH_LS1043A 199 default "fsl,ls1046a-pcie" if ARCH_LS1046A 200 default "fsl,ls2080a-pcie" if ARCH_LS2080A 201 default "fsl,ls1088a-pcie" if ARCH_LS1088A 202 help 203 This compatible is used to find pci controller node in Kernel DT 204 to complete fixup. 205 206 config HAS_FEATURE_GIC64K_ALIGN 207 bool 208 default y if ARCH_LS1043A 209 210 config HAS_FEATURE_ENHANCED_MSI 211 bool 212 default y if ARCH_LS1043A 213 214 menu "Layerscape PPA" 215 config FSL_LS_PPA 216 bool "FSL Layerscape PPA firmware support" 217 depends on !ARMV8_PSCI 218 select ARMV8_SEC_FIRMWARE_SUPPORT 219 select SEC_FIRMWARE_ARMV8_PSCI 220 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 221 help 222 The FSL Primary Protected Application (PPA) is a software component 223 which is loaded during boot stage, and then remains resident in RAM 224 and runs in the TrustZone after boot. 225 Say y to enable it. 226 227 config SPL_FSL_LS_PPA 228 bool "FSL Layerscape PPA firmware support for SPL build" 229 depends on !ARMV8_PSCI 230 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 231 select SEC_FIRMWARE_ARMV8_PSCI 232 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 233 help 234 The FSL Primary Protected Application (PPA) is a software component 235 which is loaded during boot stage, and then remains resident in RAM 236 and runs in the TrustZone after boot. This is to load PPA during SPL 237 stage instead of the RAM version of U-Boot. Once PPA is initialized, 238 the rest of U-Boot (including RAM version) runs at EL2. 239 choice 240 prompt "FSL Layerscape PPA firmware loading-media select" 241 depends on FSL_LS_PPA 242 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 243 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 244 default SYS_LS_PPA_FW_IN_XIP 245 246 config SYS_LS_PPA_FW_IN_XIP 247 bool "XIP" 248 help 249 Say Y here if the PPA firmware locate at XIP flash, such 250 as NOR or QSPI flash. 251 252 config SYS_LS_PPA_FW_IN_MMC 253 bool "eMMC or SD Card" 254 help 255 Say Y here if the PPA firmware locate at eMMC/SD card. 256 257 config SYS_LS_PPA_FW_IN_NAND 258 bool "NAND" 259 help 260 Say Y here if the PPA firmware locate at NAND flash. 261 262 endchoice 263 264 config LS_PPA_ESBC_HDR_SIZE 265 hex "Length of PPA ESBC header" 266 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 267 default 0x2000 268 help 269 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 270 NAND to memory to validate PPA image. 271 272 endmenu 273 274 config SYS_FSL_ERRATUM_A008997 275 bool "Workaround for USB PHY erratum A008997" 276 277 config SYS_FSL_ERRATUM_A009007 278 bool 279 help 280 Workaround for USB PHY erratum A009007 281 282 config SYS_FSL_ERRATUM_A009008 283 bool "Workaround for USB PHY erratum A009008" 284 285 config SYS_FSL_ERRATUM_A009798 286 bool "Workaround for USB PHY erratum A009798" 287 288 config SYS_FSL_ERRATUM_A010315 289 bool "Workaround for PCIe erratum A010315" 290 291 config SYS_FSL_ERRATUM_A010539 292 bool "Workaround for PIN MUX erratum A010539" 293 294 config MAX_CPUS 295 int "Maximum number of CPUs permitted for Layerscape" 296 default 4 if ARCH_LS1043A 297 default 4 if ARCH_LS1046A 298 default 16 if ARCH_LS2080A 299 default 8 if ARCH_LS1088A 300 default 1 301 help 302 Set this number to the maximum number of possible CPUs in the SoC. 303 SoCs may have multiple clusters with each cluster may have multiple 304 ports. If some ports are reserved but higher ports are used for 305 cores, count the reserved ports. This will allocate enough memory 306 in spin table to properly handle all cores. 307 308 config SECURE_BOOT 309 bool "Secure Boot" 310 help 311 Enable Freescale Secure Boot feature 312 313 config QSPI_AHB_INIT 314 bool "Init the QSPI AHB bus" 315 help 316 The default setting for QSPI AHB bus just support 3bytes addressing. 317 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 318 bus for those flashes to support the full QSPI flash size. 319 320 config SYS_CCI400_OFFSET 321 hex "Offset for CCI400 base" 322 depends on SYS_FSL_HAS_CCI400 323 default 0x3090000 if ARCH_LS1088A 324 default 0x180000 if FSL_LSCH2 325 help 326 Offset for CCI400 base 327 CCI400 base addr = CCSRBAR + CCI400_OFFSET 328 329 config SYS_FSL_IFC_BANK_COUNT 330 int "Maximum banks of Integrated flash controller" 331 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 332 default 4 if ARCH_LS1043A 333 default 4 if ARCH_LS1046A 334 default 8 if ARCH_LS2080A || ARCH_LS1088A 335 336 config SYS_FSL_HAS_CCI400 337 bool 338 339 config SYS_FSL_HAS_CCN504 340 bool 341 342 config SYS_FSL_HAS_DP_DDR 343 bool 344 345 config SYS_FSL_SRDS_1 346 bool 347 348 config SYS_FSL_SRDS_2 349 bool 350 351 config SYS_HAS_SERDES 352 bool 353 354 config FSL_TZASC_1 355 bool 356 357 config FSL_TZASC_2 358 bool 359 360 endmenu 361 362 menu "Layerscape clock tree configuration" 363 depends on FSL_LSCH2 || FSL_LSCH3 364 365 config SYS_FSL_CLK 366 bool "Enable clock tree initialization" 367 default y 368 369 config CLUSTER_CLK_FREQ 370 int "Reference clock of core cluster" 371 depends on ARCH_LS1012A 372 default 100000000 373 help 374 This number is the reference clock frequency of core PLL. 375 For most platforms, the core PLL and Platform PLL have the same 376 reference clock, but for some platforms, LS1012A for instance, 377 they are provided sepatately. 378 379 config SYS_FSL_PCLK_DIV 380 int "Platform clock divider" 381 default 1 if ARCH_LS1043A 382 default 1 if ARCH_LS1046A 383 default 1 if ARCH_LS1088A 384 default 2 385 help 386 This is the divider that is used to derive Platform clock from 387 Platform PLL, in another word: 388 Platform_clk = Platform_PLL_freq / this_divider 389 390 config SYS_FSL_DSPI_CLK_DIV 391 int "DSPI clock divider" 392 default 1 if ARCH_LS1043A 393 default 2 394 help 395 This is the divider that is used to derive DSPI clock from Platform 396 clock, in another word DSPI_clk = Platform_clk / this_divider. 397 398 config SYS_FSL_DUART_CLK_DIV 399 int "DUART clock divider" 400 default 1 if ARCH_LS1043A 401 default 2 402 help 403 This is the divider that is used to derive DUART clock from Platform 404 clock, in another word DUART_clk = Platform_clk / this_divider. 405 406 config SYS_FSL_I2C_CLK_DIV 407 int "I2C clock divider" 408 default 1 if ARCH_LS1043A 409 default 2 410 help 411 This is the divider that is used to derive I2C clock from Platform 412 clock, in another word I2C_clk = Platform_clk / this_divider. 413 414 config SYS_FSL_IFC_CLK_DIV 415 int "IFC clock divider" 416 default 1 if ARCH_LS1043A 417 default 2 418 help 419 This is the divider that is used to derive IFC clock from Platform 420 clock, in another word IFC_clk = Platform_clk / this_divider. 421 422 config SYS_FSL_LPUART_CLK_DIV 423 int "LPUART clock divider" 424 default 1 if ARCH_LS1043A 425 default 2 426 help 427 This is the divider that is used to derive LPUART clock from Platform 428 clock, in another word LPUART_clk = Platform_clk / this_divider. 429 430 config SYS_FSL_SDHC_CLK_DIV 431 int "SDHC clock divider" 432 default 1 if ARCH_LS1043A 433 default 1 if ARCH_LS1012A 434 default 2 435 help 436 This is the divider that is used to derive SDHC clock from Platform 437 clock, in another word SDHC_clk = Platform_clk / this_divider. 438 439 config SYS_FSL_QMAN_CLK_DIV 440 int "QMAN clock divider" 441 default 1 if ARCH_LS1043A 442 default 2 443 help 444 This is the divider that is used to derive QMAN clock from Platform 445 clock, in another word QMAN_clk = Platform_clk / this_divider. 446 endmenu 447 448 config RESV_RAM 449 bool 450 help 451 Reserve memory from the top, tracked by gd->arch.resv_ram. This 452 reserved RAM can be used by special driver that resides in memory 453 after U-Boot exits. It's up to implementation to allocate and allow 454 access to this reserved memory. For example, the reserved RAM can 455 be at the high end of physical memory. The reserve RAM may be 456 excluded from memory bank(s) passed to OS, or marked as reserved. 457 458 config SYS_FSL_EC1 459 bool 460 help 461 Ethernet controller 1, this is connected to MAC3. 462 Provides DPAA2 capabilities 463 464 config SYS_FSL_EC2 465 bool 466 help 467 Ethernet controller 2, this is connected to MAC4. 468 Provides DPAA2 capabilities 469 470 config SYS_FSL_ERRATUM_A008336 471 bool 472 473 config SYS_FSL_ERRATUM_A008514 474 bool 475 476 config SYS_FSL_ERRATUM_A008585 477 bool 478 479 config SYS_FSL_ERRATUM_A008850 480 bool 481 482 config SYS_FSL_ERRATUM_A009203 483 bool 484 485 config SYS_FSL_ERRATUM_A009635 486 bool 487 488 config SYS_FSL_ERRATUM_A009660 489 bool 490 491 config SYS_FSL_ERRATUM_A009929 492 bool 493 494 495 config SYS_FSL_HAS_RGMII 496 bool 497 depends on SYS_FSL_EC1 || SYS_FSL_EC2 498 499 500 config SYS_MC_RSV_MEM_ALIGN 501 hex "Management Complex reserved memory alignment" 502 depends on RESV_RAM 503 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A 504 help 505 Reserved memory needs to be aligned for MC to use. Default value 506 is 512MB. 507 508 config SPL_LDSCRIPT 509 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 510 511 config HAS_FSL_XHCI_USB 512 bool 513 default y if ARCH_LS1043A || ARCH_LS1046A 514 help 515 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 516 pins, select it when the pins are assigned to USB. 517
