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      1 // SPDX-License-Identifier: GPL-2.0+
      2 /*
      3  * Copyright 2015 Freescale Semiconductor, Inc.
      4  */
      5 
      6 #include <common.h>
      7 #include <asm/arch/fsl_serdes.h>
      8 #include <asm/arch/immap_lsch2.h>
      9 
     10 struct serdes_config {
     11 	u32 protocol;
     12 	u8 lanes[SRDS_MAX_LANES];
     13 };
     14 
     15 static struct serdes_config serdes1_cfg_tbl[] = {
     16 	/* SerDes 1 */
     17 	{0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} },
     18 	{0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
     19 	{0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} },
     20 	{0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} },
     21 	{0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
     22 	{0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
     23 	{0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
     24 		  PCIE3} },
     25 	{0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
     26 	{0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} },
     27 	{0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
     28 	{0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} },
     29 	{0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} },
     30 	{0x9998, {PCIE1, PCIE2, PCIE3, SATA1} },
     31 	{0x6058, {PCIE1, PCIE1, PCIE2, SATA1} },
     32 	{0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} },
     33 	{0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} },
     34 	{0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} },
     35 	{0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
     36 		  SGMII_FM1_DTSEC6} },
     37 	{}
     38 };
     39 
     40 static struct serdes_config *serdes_cfg_tbl[] = {
     41 	serdes1_cfg_tbl,
     42 };
     43 
     44 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
     45 {
     46 	struct serdes_config *ptr;
     47 
     48 	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
     49 		return 0;
     50 
     51 	ptr = serdes_cfg_tbl[serdes];
     52 	while (ptr->protocol) {
     53 		if (ptr->protocol == cfg)
     54 			return ptr->lanes[lane];
     55 		ptr++;
     56 	}
     57 
     58 	return 0;
     59 }
     60 
     61 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
     62 {
     63 	int i;
     64 	struct serdes_config *ptr;
     65 
     66 	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
     67 		return 0;
     68 
     69 	ptr = serdes_cfg_tbl[serdes];
     70 	while (ptr->protocol) {
     71 		if (ptr->protocol == prtcl)
     72 			break;
     73 		ptr++;
     74 	}
     75 
     76 	if (!ptr->protocol)
     77 		return 0;
     78 
     79 	for (i = 0; i < SRDS_MAX_LANES; i++) {
     80 		if (ptr->lanes[i] != NONE)
     81 			return 1;
     82 	}
     83 
     84 	return 0;
     85 }
     86