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      1 /*
      2  * Copyright (C) 2017 Marvell Technology Group Ltd.
      3  *
      4  * This file is dual-licensed: you can use it either under the terms
      5  * of the GPLv2 or the X11 license, at your option. Note that this dual
      6  * licensing only applies to this file, and not this project as a
      7  * whole.
      8  *
      9  *  a) This library is free software; you can redistribute it and/or
     10  *     modify it under the terms of the GNU General Public License as
     11  *     published by the Free Software Foundation; either version 2 of the
     12  *     License, or (at your option) any later version.
     13  *
     14  *     This library is distributed in the hope that it will be useful,
     15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     17  *     GNU General Public License for more details.
     18  *
     19  * Or, alternatively,
     20  *
     21  *  b) Permission is hereby granted, free of charge, to any person
     22  *     obtaining a copy of this software and associated documentation
     23  *     files (the "Software"), to deal in the Software without
     24  *     restriction, including without limitation the rights to use,
     25  *     copy, modify, merge, publish, distribute, sublicense, and/or
     26  *     sell copies of the Software, and to permit persons to whom the
     27  *     Software is furnished to do so, subject to the following
     28  *     conditions:
     29  *
     30  *     The above copyright notice and this permission notice shall be
     31  *     included in all copies or substantial portions of the Software.
     32  *
     33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     40  *     OTHER DEALINGS IN THE SOFTWARE.
     41  */
     42 
     43 /*
     44  * Device Tree file for Marvell Armada 7040 Development board platform
     45  * Boot device: NAND, 0xE (SW3)
     46  */
     47 
     48 #include "armada-7040.dtsi"
     49 
     50 / {
     51 	model = "Marvell Armada 7040 DB board with NAND";
     52 	compatible = "marvell,armada7040-db-nand", "marvell,armada7040-db",
     53 		     "marvell,armada7040", "marvell,armada-ap806-quad",
     54 		     "marvell,armada-ap806";
     55 
     56 	chosen {
     57 		stdout-path = "serial0:115200n8";
     58 	};
     59 
     60 	aliases {
     61 		i2c0 = &cpm_i2c0;
     62 		spi0 = &cpm_spi1;
     63 	};
     64 
     65 	memory@00000000 {
     66 		device_type = "memory";
     67 		reg = <0x0 0x0 0x0 0x80000000>;
     68 	};
     69 };
     70 
     71 &ap_pinctl {
     72 	   /* MPP Bus:
     73 	    * SDIO  [0-5]
     74 	    * UART0 [11,19]
     75 	    */
     76 		  /* 0   1   2   3   4   5   6   7   8   9 */
     77 	pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
     78 		     0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
     79 };
     80 
     81 &uart0 {
     82 	status = "okay";
     83 };
     84 
     85 
     86 &cpm_pcie2 {
     87 	status = "okay";
     88 };
     89 
     90 &cpm_i2c0 {
     91 	pinctrl-names = "default";
     92 	pinctrl-0 = <&cpm_i2c0_pins>;
     93 	status = "okay";
     94 	clock-frequency = <100000>;
     95 };
     96 
     97 &cpm_pinctl {
     98 		/* MPP Bus:
     99 		 * AUDIO   [0-5]
    100                  * GBE     [6-11]
    101 		 * SS_PWDN [12]
    102 		 * NF_RBn  [13]
    103                  * GPIO    [14]
    104 		 * DEV_BUS [15-27]
    105 		 * SATA1   [28]
    106 		 * UART0   [29-30]
    107 		 * MSS_VTT_EN [31]
    108 		 * SMI	   [32,34]
    109 		 * XSMI    [35-36]
    110 		 * I2C	   [37-38]
    111 		 * RGMII1  [44-55]
    112 		 * SD	   [56-61]
    113 		 * GPIO    [62]
    114 		 */
    115 		 /*   0   1   2   3   4   5   6   7   8   9 */
    116 	 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
    117 		      0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
    118 		      0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa
    119 		      0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
    120 		      0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1
    121 		      0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
    122 		      0xe 0xe 0x0>;
    123 };
    124 
    125 &cpm_spi1 {
    126 	pinctrl-names = "default";
    127 	pinctrl-0 = <&cpm_spi0_pins>;
    128 	status = "disabled";
    129 
    130 	spi-flash@0 {
    131 		#address-cells = <0x1>;
    132 		#size-cells = <0x1>;
    133 		compatible = "jedec,spi-nor";
    134 		reg = <0x0>;
    135 		spi-max-frequency = <20000000>;
    136 
    137 		partitions {
    138 			compatible = "fixed-partitions";
    139 			#address-cells = <1>;
    140 			#size-cells = <1>;
    141 
    142 			partition@0 {
    143 				label = "U-Boot";
    144 				reg = <0x0 0x200000>;
    145 			};
    146 
    147 			partition@400000 {
    148 				label = "Filesystem";
    149 				reg = <0x200000 0xe00000>;
    150 			};
    151 		};
    152 	};
    153 };
    154 
    155 &cpm_sata0 {
    156 	status = "okay";
    157 };
    158 
    159 &cpm_usb3_0 {
    160 	status = "okay";
    161 };
    162 
    163 &cpm_usb3_1 {
    164 	status = "okay";
    165 };
    166 
    167 &cpm_comphy {
    168 	phy0 {
    169 		phy-type = <PHY_TYPE_SGMII2>;
    170 		phy-speed = <PHY_SPEED_3_125G>;
    171 	};
    172 
    173 	phy1 {
    174 		phy-type = <PHY_TYPE_USB3_HOST0>;
    175 		phy-speed = <PHY_SPEED_5G>;
    176 	};
    177 
    178 	phy2 {
    179 		phy-type = <PHY_TYPE_SGMII0>;
    180 		phy-speed = <PHY_SPEED_1_25G>;
    181 	};
    182 
    183 	phy3 {
    184 		phy-type = <PHY_TYPE_SATA1>;
    185 		phy-speed = <PHY_SPEED_5G>;
    186 	};
    187 
    188 	phy4 {
    189 		phy-type = <PHY_TYPE_USB3_HOST1>;
    190 		phy-speed = <PHY_SPEED_5G>;
    191 	};
    192 
    193 	phy5 {
    194 		phy-type = <PHY_TYPE_PEX2>;
    195 		phy-speed = <PHY_SPEED_5G>;
    196 	};
    197 };
    198 
    199 &cpm_nand {
    200 	status = "okay";
    201 };
    202 
    203 &cpm_utmi0 {
    204 	status = "okay";
    205 };
    206 
    207 &cpm_utmi1 {
    208 	status = "okay";
    209 };
    210 
    211 &ap_sdhci0 {
    212 	status = "okay";
    213 	bus-width = <4>;
    214 	no-1-8-v;
    215 	non-removable;
    216 };
    217 
    218 &cpm_sdhci0 {
    219 	status = "okay";
    220 	bus-width = <4>;
    221 	no-1-8-v;
    222 	non-removable;
    223 };
    224