1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SAMSUNG/GOOGLE Peach-Pit board device tree source 4 * 5 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 */ 8 9 /dts-v1/; 10 #include "exynos54xx.dtsi" 11 #include <dt-bindings/clock/maxim,max77802.h> 12 #include <dt-bindings/regulator/maxim,max77802.h> 13 14 / { 15 model = "Samsung/Google Peach Pit board based on Exynos5420"; 16 17 compatible = "google,pit-rev#", "google,pit", 18 "google,peach", "samsung,exynos5420", "samsung,exynos5"; 19 20 config { 21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; 22 hwid = "PIT TEST A-A 7848"; 23 lazy-init = <1>; 24 }; 25 26 aliases { 27 serial0 = "/serial@12C30000"; 28 console = "/serial@12C30000"; 29 pmic = "/i2c@12CA0000"; 30 i2c104 = &i2c_tunnel; 31 }; 32 33 backlight: backlight { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm 0 1000000 0>; 36 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; 37 default-brightness-level = <7>; 38 power-supply = <&tps65090_fet1>; 39 }; 40 41 dmc { 42 mem-manuf = "samsung"; 43 mem-type = "ddr3"; 44 clock-frequency = <800000000>; 45 arm-frequency = <900000000>; 46 }; 47 48 tmu@10060000 { 49 samsung,min-temp = <25>; 50 samsung,max-temp = <125>; 51 samsung,start-warning = <95>; 52 samsung,start-tripping = <105>; 53 samsung,hw-tripping = <110>; 54 samsung,efuse-min-value = <40>; 55 samsung,efuse-value = <55>; 56 samsung,efuse-max-value = <100>; 57 samsung,slope = <274761730>; 58 samsung,dc-value = <25>; 59 }; 60 61 /* MAX77802 is on i2c bus 4 */ 62 i2c@12CA0000 { 63 clock-frequency = <400000>; 64 power-regulator@9 { 65 compatible = "maxim,max77802-pmic"; 66 reg = <0x9>; 67 }; 68 }; 69 70 i2c@12CD0000 { /* i2c7 */ 71 clock-frequency = <100000>; 72 soundcodec@20 { 73 reg = <0x20>; 74 compatible = "maxim,max98090-codec"; 75 }; 76 77 edp-lvds-bridge@48 { 78 compatible = "parade,ps8625"; 79 reg = <0x48>; 80 sleep-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; 81 reset-gpios = <&gpy7 7 GPIO_ACTIVE_LOW>; 82 parade,regs = /bits/ 8 < 83 0x02 0xa1 0x01 /* HPD low */ 84 /* 85 * SW setting 86 * [1:0] SW output 1.2V voltage is lower to 96% 87 */ 88 0x04 0x14 0x01 89 /* 90 * RCO SS setting 91 * [5:4] = b01 0.5%, b10 1%, b11 1.5% 92 */ 93 0x04 0xe3 0x20 94 0x04 0xe2 0x80 /* [7] RCO SS enable */ 95 /* 96 * RPHY Setting 97 * [3:2] CDR tune wait cycle before 98 * measure for fine tune b00: 1us, 99 * 01: 0.5us, 10:2us, 11:4us. 100 */ 101 0x04 0x8a 0x0c 102 0x04 0x89 0x08 /* [3] RFD always on */ 103 /* 104 * CTN lock in/out: 105 * 20000ppm/80000ppm. Lock out 2 106 * times. 107 */ 108 0x04 0x71 0x2d 109 /* 110 * 2.7G CDR settings 111 * NOF=40LSB for HBR CDR setting 112 */ 113 0x04 0x7d 0x07 114 0x04 0x7b 0x00 /* [1:0] Fmin=+4bands */ 115 0x04 0x7a 0xfd /* [7:5] DCO_FTRNG=+-40% */ 116 /* 117 * 1.62G CDR settings 118 * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 119 */ 120 0x04 0xc0 0x12 121 0x04 0xc1 0x92 /* Gitune=-37% */ 122 0x04 0xc2 0x1c /* Fbstep=100% */ 123 0x04 0x32 0x80 /* [7]LOS signal disable */ 124 /* 125 * RPIO Setting 126 * [7:4] LVDS driver bias current : 127 * 75% (250mV swing) 128 */ 129 0x04 0x00 0xb0 130 /* 131 * [7:6] Right-bar GPIO output strength is 8mA 132 */ 133 0x04 0x15 0x40 134 /* EQ Training State Machine Setting */ 135 0x04 0x54 0x10 /* RCO calibration start */ 136 /* [4:0] MAX_LANE_COUNT set to one lane */ 137 0x01 0x02 0x81 138 /* [4:0] LANE_COUNT_SET set to one lane */ 139 0x01 0x21 0x81 140 0x00 0x52 0x20 141 0x00 0xf1 0x03 /* HPD CP toggle enable */ 142 0x00 0x62 0x41 143 /* Counter number add 1ms counter delay */ 144 0x00 0xf6 0x01 145 /* 146 * [6]PWM function control by 147 * DPCD0040f[7], default is PWM 148 * block always works. 149 */ 150 0x00 0x77 0x06 151 /* 152 * 04h Adjust VTotal tolerance to 153 * fix the 30Hz no display issue 154 */ 155 0x00 0x4c 0x04 156 /* DPCD00400='h00, Parade OUI = 'h001cf8 */ 157 0x01 0xc0 0x00 158 0x01 0xc1 0x1c /* DPCD00401='h1c */ 159 0x01 0xc2 0xf8 /* DPCD00402='hf8 */ 160 /* 161 * DPCD403~408 = ASCII code 162 * D2SLV5='h4432534c5635 163 */ 164 0x01 0xc3 0x44 165 0x01 0xc4 0x32 /* DPCD404 */ 166 0x01 0xc5 0x53 /* DPCD405 */ 167 0x01 0xc6 0x4c /* DPCD406 */ 168 0x01 0xc7 0x56 /* DPCD407 */ 169 0x01 0xc8 0x35 /* DPCD408 */ 170 /* 171 * DPCD40A, Initial Code major revision 172 * '01' 173 */ 174 0x01 0xca 0x01 175 /* DPCD40B Initial Code minor revision '05' */ 176 0x01 0xcb 0x05 177 /* DPCD720 Select internal PWM */ 178 0x01 0xa5 0xa0 179 /* 180 * FFh for 100% PWM of brightness, 0h for 0% 181 * brightness 182 */ 183 0x01 0xa7 0xff 184 /* 185 * Set LVDS output as 6bit-VESA mapping, 186 * single LVDS channel 187 */ 188 0x01 0xcc 0x13 189 /* Enable SSC set by register */ 190 0x02 0xb1 0x20 191 /* 192 * Set SSC enabled and +/-1% central 193 * spreading 194 */ 195 0x04 0x10 0x16 196 /* MPU Clock source: LC => RCO */ 197 0x04 0x59 0x60 198 0x04 0x54 0x14 /* LC -> RCO */ 199 0x02 0xa1 0x91>; /* HPD high */ 200 201 ports { 202 port@0 { 203 bridge_out: endpoint { 204 remote-endpoint = <&panel_in>; 205 }; 206 }; 207 208 port@1 { 209 bridge_in: endpoint { 210 remote-endpoint = <&dp_out>; 211 }; 212 }; 213 }; 214 }; 215 }; 216 217 sound@3830000 { 218 samsung,codec-type = "max98090"; 219 }; 220 221 i2c@12E10000 { /* i2c9 */ 222 clock-frequency = <400000>; 223 tpm@20 { 224 compatible = "infineon,slb9645tt"; 225 reg = <0x20>; 226 }; 227 }; 228 229 panel: panel { 230 compatible = "auo,b116xw03"; 231 power-supply = <&tps65090_fet6>; 232 backlight = <&backlight>; 233 234 port { 235 panel_in: endpoint { 236 remote-endpoint = <&bridge_out>; 237 }; 238 }; 239 }; 240 241 spi@12d30000 { /* spi1 */ 242 spi-max-frequency = <50000000>; 243 firmware_storage_spi: flash@0 { 244 compatible = "spi-flash"; 245 reg = <0>; 246 247 /* 248 * A region for the kernel to store a panic event 249 * which the firmware will add to the log. 250 */ 251 elog-panic-event-offset = <0x01e00000 0x100000>; 252 253 elog-shrink-size = <0x400>; 254 elog-full-threshold = <0xc00>; 255 }; 256 }; 257 258 xhci@12000000 { 259 samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; 260 }; 261 262 xhci@12400000 { 263 samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; 264 }; 265 266 fimd@14400000 { 267 samsung,vl-freq = <60>; 268 samsung,vl-col = <1366>; 269 samsung,vl-row = <768>; 270 samsung,vl-width = <1366>; 271 samsung,vl-height = <768>; 272 273 samsung,vl-clkp; 274 samsung,vl-dp; 275 samsung,vl-bpix = <4>; 276 277 samsung,vl-hspw = <32>; 278 samsung,vl-hbpd = <40>; 279 samsung,vl-hfpd = <40>; 280 samsung,vl-vspw = <6>; 281 samsung,vl-vbpd = <10>; 282 samsung,vl-vfpd = <12>; 283 samsung,vl-cmd-allow-len = <0xf>; 284 285 samsung,winid = <3>; 286 samsung,interface-mode = <1>; 287 samsung,dp-enabled = <1>; 288 samsung,dual-lcd-enabled = <0>; 289 }; 290 }; 291 292 &dp { 293 status = "okay"; 294 samsung,color-space = <0>; 295 samsung,dynamic-range = <0>; 296 samsung,ycbcr-coeff = <0>; 297 samsung,color-depth = <1>; 298 samsung,link-rate = <0x06>; 299 samsung,lane-count = <2>; 300 samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; 301 302 ports { 303 port@0 { 304 dp_out: endpoint { 305 remote-endpoint = <&bridge_in>; 306 }; 307 }; 308 }; 309 }; 310 311 &spi_2 { 312 spi-max-frequency = <3125000>; 313 spi-deactivate-delay = <200>; 314 status = "okay"; 315 num-cs = <1>; 316 samsung,spi-src-clk = <0>; 317 cs-gpios = <&gpb1 2 0>; 318 319 cros_ec: cros-ec@0 { 320 compatible = "google,cros-ec-spi"; 321 interrupt-parent = <&gpx1>; 322 interrupts = <5 0>; 323 reg = <0>; 324 spi-half-duplex; 325 spi-max-timeout-ms = <1100>; 326 ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>; 327 #address-cells = <1>; 328 #size-cells = <1>; 329 330 /* 331 * This describes the flash memory within the EC. Note 332 * that the STM32L flash erases to 0, not 0xff. 333 */ 334 flash@8000000 { 335 reg = <0x08000000 0x20000>; 336 erase-value = <0>; 337 }; 338 339 controller-data { 340 samsung,spi-feedback-delay = <1>; 341 }; 342 343 i2c_tunnel: i2c-tunnel { 344 compatible = "google,cros-ec-i2c-tunnel"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 google,remote-bus = <0>; 348 349 battery: sbs-battery@b { 350 compatible = "sbs,sbs-battery"; 351 reg = <0xb>; 352 sbs,poll-retry-count = <1>; 353 sbs,i2c-retry-count = <2>; 354 }; 355 356 power-regulator@48 { 357 compatible = "ti,tps65090"; 358 reg = <0x48>; 359 360 regulators { 361 tps65090_dcdc1: dcdc1 { 362 ti,enable-ext-control; 363 }; 364 tps65090_dcdc2: dcdc2 { 365 ti,enable-ext-control; 366 }; 367 tps65090_dcdc3: dcdc3 { 368 ti,enable-ext-control; 369 }; 370 tps65090_fet1: fet1 { 371 regulator-name = "vcd_led"; 372 }; 373 tps65090_fet2: fet2 { 374 regulator-name = "video_mid"; 375 regulator-always-on; 376 }; 377 tps65090_fet3: fet3 { 378 regulator-name = "wwan_r"; 379 regulator-always-on; 380 }; 381 tps65090_fet4: fet4 { 382 regulator-name = "sdcard"; 383 regulator-always-on; 384 }; 385 tps65090_fet5: fet5 { 386 regulator-name = "camout"; 387 regulator-always-on; 388 }; 389 tps65090_fet6: fet6 { 390 regulator-name = "lcd_vdd"; 391 }; 392 tps65090_fet7: fet7 { 393 regulator-name = "video_mid_1a"; 394 regulator-always-on; 395 }; 396 tps65090_ldo1: ldo1 { 397 }; 398 tps65090_ldo2: ldo2 { 399 }; 400 }; 401 402 charger { 403 compatible = "ti,tps65090-charger"; 404 }; 405 }; 406 }; 407 }; 408 }; 409 410 #include "cros-ec-keyboard.dtsi" 411
