1 // SPDX-License-Identifier: GPL-2.0+ OR X11 2 /* 3 * Copyright 2016 Beckhoff Automation 4 * Copyright 2011 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8 /dts-v1/; 9 #include "imx53.dtsi" 10 11 #define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 12 #define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 13 #define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 14 #define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 15 16 / { 17 model = "Beckhoff CX9020-0100 i.MX53"; 18 compatible = "fsl,imx53-qsb", "fsl,imx53"; 19 20 chosen { 21 stdout-path = &uart2; 22 }; 23 }; 24 25 &iomuxc { 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_hog>; 28 29 imx53-qsb { 30 pinctrl_hog: hoggrp { 31 fsl,pins = < 32 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 33 MX53_PAD_GPIO_8__GPIO1_8 0x80000000 34 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 35 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 36 MX53_PAD_GPIO_1__GPIO1_1 0x80000000 37 MX53_PAD_GPIO_4__GPIO1_4 0x80000000 38 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 39 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 40 MX53_PAD_GPIO_16__GPIO7_11 0x80000000 41 42 MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 43 MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x80000000 44 MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x80000000 45 MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 46 MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x80000000 47 MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x80000000 48 MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x80000000 49 MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x80000000 50 MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x80000000 51 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 52 MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x80000000 53 MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x80000000 54 MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x80000000 55 MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x80000000 56 MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x80000000 57 MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x80000000 58 MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x80000000 59 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 60 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 61 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 62 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 63 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 64 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 65 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 66 MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 67 MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0xa4 68 MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0xa4 69 MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0xa4 70 MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0xa4 71 MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0xa4 72 MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0xa4 73 MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0xa4 74 MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0xa4 75 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 76 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 77 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 78 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 79 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 80 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 81 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 82 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 83 MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0xa4 84 MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0xa4 85 MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0xa4 86 MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0xa4 87 MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0xa4 88 MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0xa4 89 MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0xa4 90 MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0xa4 91 MX53_PAD_NANDF_CLE__GPIO6_7 0x00000001 92 MX53_PAD_NANDF_WP_B__GPIO6_9 0x00000001 93 MX53_PAD_NANDF_ALE__GPIO6_8 0x00000001 94 95 MX53_PAD_EIM_D23__GPIO3_23 0x80000000 96 97 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 98 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 99 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 100 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 101 102 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 103 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 104 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 105 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 106 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 107 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 108 109 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 110 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 111 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 112 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 113 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 114 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 115 116 MX53_PAD_FEC_MDC__FEC_MDC 0x4 117 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc 118 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 119 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 120 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 121 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 122 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 123 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 124 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 125 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 126 127 MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec 128 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec 129 130 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 131 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 132 133 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 134 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 135 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 136 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 137 MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5 138 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 139 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 140 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 141 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 142 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 143 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 144 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 145 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 146 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 147 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 148 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 149 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 150 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 151 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 152 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 153 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 154 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 155 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 156 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 157 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 158 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 159 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 160 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 161 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 162 >; 163 }; 164 165 pinctrl_uart2: uart2grp { 166 fsl,pins = < 167 MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4 168 MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4 169 MX53_PAD_EIM_D28__UART2_RTS 0x1e4 170 MX53_PAD_EIM_D29__UART2_CTS 0x1e4 171 >; 172 }; 173 }; 174 }; 175 176 &uart2 { 177 pinctrl-names = "default"; 178 uart-has-rtscts; 179 fsl,dte-mode; 180 pinctrl-0 = <&pinctrl_uart2>; 181 status = "okay"; 182 }; 183 184 &fec { 185 pinctrl-names = "default"; 186 phy-mode = "rmii"; 187 phy-reset-gpios = <&gpio7 6 0>; 188 status = "okay"; 189 }; 190
