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      1 
      2 /*
      3  * Copyright 2013 Freescale Semiconductor, Inc.
      4  *
      5  * This program is free software; you can redistribute it and/or modify
      6  * it under the terms of the GNU General Public License version 2 as
      7  * published by the Free Software Foundation.
      8  *
      9  */
     10 
     11 #include <dt-bindings/interrupt-controller/irq.h>
     12 #include "imx6dl-pinfunc.h"
     13 #include "imx6qdl.dtsi"
     14 
     15 / {
     16 	aliases {
     17 		i2c3 = &i2c4;
     18 	};
     19 
     20 	cpus {
     21 		#address-cells = <1>;
     22 		#size-cells = <0>;
     23 
     24 		cpu@0 {
     25 			compatible = "arm,cortex-a9";
     26 			device_type = "cpu";
     27 			reg = <0>;
     28 			next-level-cache = <&L2>;
     29 			operating-points = <
     30 				/* kHz    uV */
     31 				996000  1250000
     32 				792000  1175000
     33 				396000  1150000
     34 			>;
     35 			fsl,soc-operating-points = <
     36 				/* ARM kHz  SOC-PU uV */
     37 				996000	1175000
     38 				792000	1175000
     39 				396000	1175000
     40 			>;
     41 			clock-latency = <61036>; /* two CLK32 periods */
     42 			clocks = <&clks IMX6QDL_CLK_ARM>,
     43 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
     44 				 <&clks IMX6QDL_CLK_STEP>,
     45 				 <&clks IMX6QDL_CLK_PLL1_SW>,
     46 				 <&clks IMX6QDL_CLK_PLL1_SYS>;
     47 			clock-names = "arm", "pll2_pfd2_396m", "step",
     48 				      "pll1_sw", "pll1_sys";
     49 			arm-supply = <&reg_arm>;
     50 			pu-supply = <&reg_pu>;
     51 			soc-supply = <&reg_soc>;
     52 		};
     53 
     54 		cpu@1 {
     55 			compatible = "arm,cortex-a9";
     56 			device_type = "cpu";
     57 			reg = <1>;
     58 			next-level-cache = <&L2>;
     59 		};
     60 	};
     61 
     62 	soc {
     63 		ocram: sram@00900000 {
     64 			compatible = "mmio-sram";
     65 			reg = <0x00900000 0x20000>;
     66 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
     67 		};
     68 
     69 		aips1: aips-bus@02000000 {
     70 			iomuxc: iomuxc@020e0000 {
     71 				compatible = "fsl,imx6dl-iomuxc";
     72 			};
     73 
     74 			pxp: pxp@020f0000 {
     75 				reg = <0x020f0000 0x4000>;
     76 				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
     77 			};
     78 
     79 			epdc: epdc@020f4000 {
     80 				reg = <0x020f4000 0x4000>;
     81 				interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
     82 			};
     83 
     84 			lcdif: lcdif@020f8000 {
     85 				reg = <0x020f8000 0x4000>;
     86 				interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
     87 			};
     88 		};
     89 
     90 		aips2: aips-bus@02100000 {
     91 			i2c4: i2c@021f8000 {
     92 				#address-cells = <1>;
     93 				#size-cells = <0>;
     94 				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
     95 				reg = <0x021f8000 0x4000>;
     96 				interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
     97 				clocks = <&clks IMX6DL_CLK_I2C4>;
     98 				status = "disabled";
     99 			};
    100 		};
    101 	};
    102 
    103 	display-subsystem {
    104 		compatible = "fsl,imx-display-subsystem";
    105 		ports = <&ipu1_di0>, <&ipu1_di1>;
    106 	};
    107 
    108 	gpu-subsystem {
    109 		compatible = "fsl,imx-gpu-subsystem";
    110 		cores = <&gpu_2d>, <&gpu_3d>;
    111 	};
    112 };
    113 
    114 &gpt {
    115 	compatible = "fsl,imx6dl-gpt";
    116 };
    117 
    118 &hdmi {
    119 	compatible = "fsl,imx6dl-hdmi";
    120 };
    121 
    122 &ldb {
    123 	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
    124 		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
    125 		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
    126 	clock-names = "di0_pll", "di1_pll",
    127 		      "di0_sel", "di1_sel",
    128 		      "di0", "di1";
    129 };
    130 
    131 &vpu {
    132 	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
    133 };
    134