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      1 
      2 /*
      3  * Copyright 2013 Freescale Semiconductor, Inc.
      4  *
      5  * This program is free software; you can redistribute it and/or modify
      6  * it under the terms of the GNU General Public License version 2 as
      7  * published by the Free Software Foundation.
      8  *
      9  */
     10 
     11 #include <dt-bindings/interrupt-controller/irq.h>
     12 #include "imx6q-pinfunc.h"
     13 #include "imx6qdl.dtsi"
     14 
     15 / {
     16 	aliases {
     17 		ipu1 = &ipu2;
     18 		spi4 = &ecspi5;
     19 	};
     20 
     21 	cpus {
     22 		#address-cells = <1>;
     23 		#size-cells = <0>;
     24 
     25 		cpu0: cpu@0 {
     26 			compatible = "arm,cortex-a9";
     27 			device_type = "cpu";
     28 			reg = <0>;
     29 			next-level-cache = <&L2>;
     30 			operating-points = <
     31 				/* kHz    uV */
     32 				1200000 1275000
     33 				996000  1250000
     34 				852000  1250000
     35 				792000  1175000
     36 				396000  975000
     37 			>;
     38 			fsl,soc-operating-points = <
     39 				/* ARM kHz  SOC-PU uV */
     40 				1200000 1275000
     41 				996000	1250000
     42 				852000	1250000
     43 				792000	1175000
     44 				396000	1175000
     45 			>;
     46 			clock-latency = <61036>; /* two CLK32 periods */
     47 			clocks = <&clks IMX6QDL_CLK_ARM>,
     48 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
     49 				 <&clks IMX6QDL_CLK_STEP>,
     50 				 <&clks IMX6QDL_CLK_PLL1_SW>,
     51 				 <&clks IMX6QDL_CLK_PLL1_SYS>;
     52 			clock-names = "arm", "pll2_pfd2_396m", "step",
     53 				      "pll1_sw", "pll1_sys";
     54 			arm-supply = <&reg_arm>;
     55 			pu-supply = <&reg_pu>;
     56 			soc-supply = <&reg_soc>;
     57 		};
     58 
     59 		cpu@1 {
     60 			compatible = "arm,cortex-a9";
     61 			device_type = "cpu";
     62 			reg = <1>;
     63 			next-level-cache = <&L2>;
     64 		};
     65 
     66 		cpu@2 {
     67 			compatible = "arm,cortex-a9";
     68 			device_type = "cpu";
     69 			reg = <2>;
     70 			next-level-cache = <&L2>;
     71 		};
     72 
     73 		cpu@3 {
     74 			compatible = "arm,cortex-a9";
     75 			device_type = "cpu";
     76 			reg = <3>;
     77 			next-level-cache = <&L2>;
     78 		};
     79 	};
     80 
     81 	soc {
     82 		ocram: sram@00900000 {
     83 			compatible = "mmio-sram";
     84 			reg = <0x00900000 0x40000>;
     85 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
     86 		};
     87 
     88 		aips-bus@02000000 { /* AIPS1 */
     89 			spba-bus@02000000 {
     90 				ecspi5: ecspi@02018000 {
     91 					#address-cells = <1>;
     92 					#size-cells = <0>;
     93 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
     94 					reg = <0x02018000 0x4000>;
     95 					interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
     96 					clocks = <&clks IMX6Q_CLK_ECSPI5>,
     97 						 <&clks IMX6Q_CLK_ECSPI5>;
     98 					clock-names = "ipg", "per";
     99 					dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
    100 					dma-names = "rx", "tx";
    101 					status = "disabled";
    102 				};
    103 			};
    104 
    105 			iomuxc: iomuxc@020e0000 {
    106 				compatible = "fsl,imx6q-iomuxc";
    107 			};
    108 		};
    109 
    110 		sata: sata@02200000 {
    111 			compatible = "fsl,imx6q-ahci";
    112 			reg = <0x02200000 0x4000>;
    113 			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
    114 			clocks = <&clks IMX6QDL_CLK_SATA>,
    115 				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
    116 				 <&clks IMX6QDL_CLK_AHB>;
    117 			clock-names = "sata", "sata_ref", "ahb";
    118 			status = "disabled";
    119 		};
    120 
    121 		gpu_vg: gpu@02204000 {
    122 			compatible = "vivante,gc";
    123 			reg = <0x02204000 0x4000>;
    124 			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
    125 			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
    126 				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
    127 			clock-names = "bus", "core";
    128 			power-domains = <&gpc 1>;
    129 		};
    130 
    131 		ipu2: ipu@02800000 {
    132 			#address-cells = <1>;
    133 			#size-cells = <0>;
    134 			compatible = "fsl,imx6q-ipu";
    135 			reg = <0x02800000 0x400000>;
    136 			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
    137 				     <0 7 IRQ_TYPE_LEVEL_HIGH>;
    138 			clocks = <&clks IMX6QDL_CLK_IPU2>,
    139 				 <&clks IMX6QDL_CLK_IPU2_DI0>,
    140 				 <&clks IMX6QDL_CLK_IPU2_DI1>;
    141 			clock-names = "bus", "di0", "di1";
    142 			resets = <&src 4>;
    143 
    144 			ipu2_csi0: port@0 {
    145 				reg = <0>;
    146 			};
    147 
    148 			ipu2_csi1: port@1 {
    149 				reg = <1>;
    150 			};
    151 
    152 			ipu2_di0: port@2 {
    153 				#address-cells = <1>;
    154 				#size-cells = <0>;
    155 				reg = <2>;
    156 
    157 				ipu2_di0_disp0: disp0-endpoint {
    158 				};
    159 
    160 				ipu2_di0_hdmi: hdmi-endpoint {
    161 					remote-endpoint = <&hdmi_mux_2>;
    162 				};
    163 
    164 				ipu2_di0_mipi: mipi-endpoint {
    165 					remote-endpoint = <&mipi_mux_2>;
    166 				};
    167 
    168 				ipu2_di0_lvds0: lvds0-endpoint {
    169 					remote-endpoint = <&lvds0_mux_2>;
    170 				};
    171 
    172 				ipu2_di0_lvds1: lvds1-endpoint {
    173 					remote-endpoint = <&lvds1_mux_2>;
    174 				};
    175 			};
    176 
    177 			ipu2_di1: port@3 {
    178 				#address-cells = <1>;
    179 				#size-cells = <0>;
    180 				reg = <3>;
    181 
    182 				ipu2_di1_hdmi: hdmi-endpoint {
    183 					remote-endpoint = <&hdmi_mux_3>;
    184 				};
    185 
    186 				ipu2_di1_mipi: mipi-endpoint {
    187 					remote-endpoint = <&mipi_mux_3>;
    188 				};
    189 
    190 				ipu2_di1_lvds0: lvds0-endpoint {
    191 					remote-endpoint = <&lvds0_mux_3>;
    192 				};
    193 
    194 				ipu2_di1_lvds1: lvds1-endpoint {
    195 					remote-endpoint = <&lvds1_mux_3>;
    196 				};
    197 			};
    198 		};
    199 	};
    200 
    201 	display-subsystem {
    202 		compatible = "fsl,imx-display-subsystem";
    203 		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
    204 	};
    205 
    206 	gpu-subsystem {
    207 		compatible = "fsl,imx-gpu-subsystem";
    208 		cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
    209 	};
    210 };
    211 
    212 &hdmi {
    213 	compatible = "fsl,imx6q-hdmi";
    214 
    215 	port@2 {
    216 		reg = <2>;
    217 
    218 		hdmi_mux_2: endpoint {
    219 			remote-endpoint = <&ipu2_di0_hdmi>;
    220 		};
    221 	};
    222 
    223 	port@3 {
    224 		reg = <3>;
    225 
    226 		hdmi_mux_3: endpoint {
    227 			remote-endpoint = <&ipu2_di1_hdmi>;
    228 		};
    229 	};
    230 };
    231 
    232 &ldb {
    233 	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
    234 		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
    235 		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
    236 		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
    237 	clock-names = "di0_pll", "di1_pll",
    238 		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
    239 		      "di0", "di1";
    240 
    241 	lvds-channel@0 {
    242 		port@2 {
    243 			reg = <2>;
    244 
    245 			lvds0_mux_2: endpoint {
    246 				remote-endpoint = <&ipu2_di0_lvds0>;
    247 			};
    248 		};
    249 
    250 		port@3 {
    251 			reg = <3>;
    252 
    253 			lvds0_mux_3: endpoint {
    254 				remote-endpoint = <&ipu2_di1_lvds0>;
    255 			};
    256 		};
    257 	};
    258 
    259 	lvds-channel@1 {
    260 		port@2 {
    261 			reg = <2>;
    262 
    263 			lvds1_mux_2: endpoint {
    264 				remote-endpoint = <&ipu2_di0_lvds1>;
    265 			};
    266 		};
    267 
    268 		port@3 {
    269 			reg = <3>;
    270 
    271 			lvds1_mux_3: endpoint {
    272 				remote-endpoint = <&ipu2_di1_lvds1>;
    273 			};
    274 		};
    275 	};
    276 };
    277 
    278 &mipi_dsi {
    279 	ports {
    280 		port@2 {
    281 			reg = <2>;
    282 
    283 			mipi_mux_2: endpoint {
    284 				remote-endpoint = <&ipu2_di0_mipi>;
    285 			};
    286 		};
    287 
    288 		port@3 {
    289 			reg = <3>;
    290 
    291 			mipi_mux_3: endpoint {
    292 				remote-endpoint = <&ipu2_di1_mipi>;
    293 			};
    294 		};
    295 	};
    296 };
    297 
    298 &vpu {
    299 	compatible = "fsl,imx6q-vpu", "cnm,coda960";
    300 };
    301