1 /* 2 * Copyright 2015-2016 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <dt-bindings/clock/imx6ul-clock.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/input/input.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include "imx6ull-pinfunc.h" 14 #include "imx6ull-pinfunc-snvs.h" 15 #include "skeleton.dtsi" 16 17 / { 18 aliases { 19 can0 = &flexcan1; 20 can1 = &flexcan2; 21 ethernet0 = &fec1; 22 ethernet1 = &fec2; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 serial0 = &uart1; 35 serial1 = &uart2; 36 serial2 = &uart3; 37 serial3 = &uart4; 38 serial4 = &uart5; 39 serial5 = &uart6; 40 serial6 = &uart7; 41 serial7 = &uart8; 42 spi0 = &qspi; 43 spi1 = &ecspi1; 44 spi2 = &ecspi2; 45 spi3 = &ecspi3; 46 spi4 = &ecspi4; 47 usbphy0 = &usbphy1; 48 usbphy1 = &usbphy2; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 cpu0: cpu@0 { 56 compatible = "arm,cortex-a7"; 57 device_type = "cpu"; 58 reg = <0>; 59 clock-latency = <61036>; /* two CLK32 periods */ 60 operating-points = < 61 /* kHz uV */ 62 528000 1175000 63 99000 950000 64 >; 65 fsl,soc-operating-points = < 66 /* KHz uV */ 67 528000 1175000 68 99000 1175000 69 >; 70 clocks = <&clks IMX6UL_CLK_ARM>, 71 <&clks IMX6UL_CLK_PLL2_BUS>, 72 <&clks IMX6UL_CLK_PLL2_PFD2>, 73 <&clks IMX6UL_CA7_SECONDARY_SEL>, 74 <&clks IMX6UL_CLK_STEP>, 75 <&clks IMX6UL_CLK_PLL1_SW>, 76 <&clks IMX6UL_CLK_PLL1_SYS>, 77 <&clks IMX6UL_PLL1_BYPASS>, 78 <&clks IMX6UL_CLK_PLL1>, 79 <&clks IMX6UL_PLL1_BYPASS_SRC>, 80 <&clks IMX6UL_CLK_OSC>; 81 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", 82 "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc"; 83 }; 84 }; 85 86 intc: interrupt-controller@00a01000 { 87 compatible = "arm,cortex-a7-gic"; 88 #interrupt-cells = <3>; 89 interrupt-controller; 90 reg = <0x00a01000 0x1000>, 91 <0x00a02000 0x100>; 92 }; 93 94 clocks { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 ckil: clock@0 { 99 compatible = "fixed-clock"; 100 reg = <0>; 101 #clock-cells = <0>; 102 clock-frequency = <32768>; 103 clock-output-names = "ckil"; 104 }; 105 106 osc: clock@1 { 107 compatible = "fixed-clock"; 108 reg = <1>; 109 #clock-cells = <0>; 110 clock-frequency = <24000000>; 111 clock-output-names = "osc"; 112 }; 113 114 ipp_di0: clock@2 { 115 compatible = "fixed-clock"; 116 reg = <2>; 117 #clock-cells = <0>; 118 clock-frequency = <0>; 119 clock-output-names = "ipp_di0"; 120 }; 121 122 ipp_di1: clock@3 { 123 compatible = "fixed-clock"; 124 reg = <3>; 125 #clock-cells = <0>; 126 clock-frequency = <0>; 127 clock-output-names = "ipp_di1"; 128 }; 129 }; 130 131 soc { 132 #address-cells = <1>; 133 #size-cells = <1>; 134 compatible = "simple-bus"; 135 interrupt-parent = <&gpc>; 136 ranges; 137 138 busfreq { 139 compatible = "fsl,imx_busfreq"; 140 clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>, 141 <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>, 142 <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>, 143 <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>, 144 <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>, 145 <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>, 146 <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>, 147 <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>, 148 <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>, 149 <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>, 150 <&clks IMX6UL_CLK_PLL1>; 151 clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", 152 "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", 153 "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", 154 "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; 155 fsl,max_ddr_freq = <400000000>; 156 }; 157 158 pmu { 159 compatible = "arm,cortex-a7-pmu"; 160 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 161 status = "disabled"; 162 }; 163 164 ocrams: sram@00900000 { 165 compatible = "fsl,lpm-sram"; 166 reg = <0x00900000 0x4000>; 167 }; 168 169 ocrams_ddr: sram@00904000 { 170 compatible = "fsl,ddr-lpm-sram"; 171 reg = <0x00904000 0x1000>; 172 }; 173 174 ocram: sram@00905000 { 175 compatible = "mmio-sram"; 176 reg = <0x00905000 0x1B000>; 177 }; 178 179 dma_apbh: dma-apbh@01804000 { 180 compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh"; 181 reg = <0x01804000 0x2000>; 182 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 186 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 187 #dma-cells = <1>; 188 dma-channels = <4>; 189 clocks = <&clks IMX6UL_CLK_APBHDMA>; 190 }; 191 192 gpmi: gpmi-nand@01806000{ 193 compatible = "fsl,imx6ull-gpmi-nand", "fsl, imx6ul-gpmi-nand"; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 reg = <0x01806000 0x2000>, <0x01808000 0x4000>; 197 reg-names = "gpmi-nand", "bch"; 198 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 199 interrupt-names = "bch"; 200 clocks = <&clks IMX6UL_CLK_GPMI_IO>, 201 <&clks IMX6UL_CLK_GPMI_APB>, 202 <&clks IMX6UL_CLK_GPMI_BCH>, 203 <&clks IMX6UL_CLK_GPMI_BCH_APB>, 204 <&clks IMX6UL_CLK_PER_BCH>; 205 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 206 "gpmi_bch_apb", "per1_bch"; 207 dmas = <&dma_apbh 0>; 208 dma-names = "rx-tx"; 209 status = "disabled"; 210 }; 211 212 aips1: aips-bus@02000000 { 213 compatible = "fsl,aips-bus", "simple-bus"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 reg = <0x02000000 0x100000>; 217 ranges; 218 219 spba-bus@02000000 { 220 compatible = "fsl,spba-bus", "simple-bus"; 221 #address-cells = <1>; 222 #size-cells = <1>; 223 reg = <0x02000000 0x40000>; 224 ranges; 225 226 spdif: spdif@02004000 { 227 compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif"; 228 reg = <0x02004000 0x4000>; 229 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 230 dmas = <&sdma 41 18 0>, 231 <&sdma 42 18 0>; 232 dma-names = "rx", "tx"; 233 clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>, 234 <&clks IMX6UL_CLK_OSC>, 235 <&clks IMX6UL_CLK_SPDIF>, 236 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, 237 <&clks IMX6UL_CLK_IPG>, 238 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, 239 <&clks IMX6UL_CLK_SPBA>; 240 clock-names = "core", "rxtx0", 241 "rxtx1", "rxtx2", 242 "rxtx3", "rxtx4", 243 "rxtx5", "rxtx6", 244 "rxtx7", "dma"; 245 status = "disabled"; 246 }; 247 248 ecspi1: ecspi@02008000 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 252 reg = <0x02008000 0x4000>; 253 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&clks IMX6UL_CLK_ECSPI1>, 255 <&clks IMX6UL_CLK_ECSPI1>; 256 clock-names = "ipg", "per"; 257 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 258 dma-names = "rx", "tx"; 259 status = "disabled"; 260 }; 261 262 ecspi2: ecspi@0200c000 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 266 reg = <0x0200c000 0x4000>; 267 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&clks IMX6UL_CLK_ECSPI2>, 269 <&clks IMX6UL_CLK_ECSPI2>; 270 clock-names = "ipg", "per"; 271 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 272 dma-names = "rx", "tx"; 273 status = "disabled"; 274 }; 275 276 ecspi3: ecspi@02010000 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 280 reg = <0x02010000 0x4000>; 281 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&clks IMX6UL_CLK_ECSPI3>, 283 <&clks IMX6UL_CLK_ECSPI3>; 284 clock-names = "ipg", "per"; 285 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 286 dma-names = "rx", "tx"; 287 status = "disabled"; 288 }; 289 290 ecspi4: ecspi@02014000 { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 294 reg = <0x02014000 0x4000>; 295 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&clks IMX6UL_CLK_ECSPI4>, 297 <&clks IMX6UL_CLK_ECSPI4>; 298 clock-names = "ipg", "per"; 299 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 300 dma-names = "rx", "tx"; 301 status = "disabled"; 302 }; 303 304 uart7: serial@02018000 { 305 compatible = "fsl,imx6ul-uart", 306 "fsl,imx6q-uart", "fsl,imx21-uart"; 307 reg = <0x02018000 0x4000>; 308 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&clks IMX6UL_CLK_UART7_IPG>, 310 <&clks IMX6UL_CLK_UART7_SERIAL>; 311 clock-names = "ipg", "per"; 312 dmas = <&sdma 43 4 0>, <&sdma 44 4 0>; 313 dma-names = "rx", "tx"; 314 status = "disabled"; 315 }; 316 317 uart1: serial@02020000 { 318 compatible = "fsl,imx6ul-uart", 319 "fsl,imx6q-uart", "fsl,imx21-uart"; 320 reg = <0x02020000 0x4000>; 321 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&clks IMX6UL_CLK_UART1_IPG>, 323 <&clks IMX6UL_CLK_UART1_SERIAL>; 324 clock-names = "ipg", "per"; 325 status = "disabled"; 326 }; 327 328 esai: esai@02024000 { 329 compatible = "fsl,imx6ull-esai"; 330 reg = <0x02024000 0x4000>; 331 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clks IMX6UL_CLK_ESAI_IPG>, 333 <&clks IMX6UL_CLK_ESAI_MEM>, 334 <&clks IMX6UL_CLK_ESAI_EXTAL>, 335 <&clks IMX6UL_CLK_ESAI_IPG>, 336 <&clks IMX6UL_CLK_SPBA>; 337 clock-names = "core", "mem", "extal", 338 "fsys", "dma"; 339 dmas = <&sdma 0 21 0>, <&sdma 47 21 0>; 340 dma-names = "rx", "tx"; 341 dma-source = <&gpr 0 14 0 15>; 342 status = "disabled"; 343 }; 344 345 sai1: sai@02028000 { 346 compatible = "fsl,imx6ul-sai", 347 "fsl,imx6sx-sai"; 348 reg = <0x02028000 0x4000>; 349 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&clks IMX6UL_CLK_SAI1_IPG>, 351 <&clks IMX6UL_CLK_DUMMY>, 352 <&clks IMX6UL_CLK_SAI1>, 353 <&clks 0>, <&clks 0>; 354 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 355 dma-names = "rx", "tx"; 356 dmas = <&sdma 35 24 0>, <&sdma 36 24 0>; 357 status = "disabled"; 358 }; 359 360 sai2: sai@0202c000 { 361 compatible = "fsl,imx6ul-sai", 362 "fsl,imx6sx-sai"; 363 reg = <0x0202c000 0x4000>; 364 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clks IMX6UL_CLK_SAI2_IPG>, 366 <&clks IMX6UL_CLK_DUMMY>, 367 <&clks IMX6UL_CLK_SAI2>, 368 <&clks 0>, <&clks 0>; 369 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 370 dma-names = "rx", "tx"; 371 dmas = <&sdma 37 24 0>, <&sdma 38 24 0>; 372 status = "disabled"; 373 }; 374 375 sai3: sai@02030000 { 376 compatible = "fsl,imx6ul-sai", 377 "fsl,imx6sx-sai"; 378 reg = <0x02030000 0x4000>; 379 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&clks IMX6UL_CLK_SAI3_IPG>, 381 <&clks IMX6UL_CLK_DUMMY>, 382 <&clks IMX6UL_CLK_SAI3>, 383 <&clks 0>, <&clks 0>; 384 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 385 dma-names = "rx", "tx"; 386 dmas = <&sdma 39 24 0>, <&sdma 40 24 0>; 387 status = "disabled"; 388 }; 389 390 asrc: asrc@02034000 { 391 compatible = "fsl,imx53-asrc"; 392 reg = <0x02034000 0x4000>; 393 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&clks IMX6UL_CLK_ASRC_IPG>, 395 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, 396 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 397 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 398 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 399 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, 400 <&clks IMX6UL_CLK_SPBA>; 401 clock-names = "mem", "ipg", "asrck_0", 402 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 403 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 404 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 405 "asrck_d", "asrck_e", "asrck_f", "dma"; 406 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, 407 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; 408 dma-names = "rxa", "rxb", "rxc", 409 "txa", "txb", "txc"; 410 fsl,asrc-rate = <48000>; 411 fsl,asrc-width = <16>; 412 status = "okay"; 413 }; 414 }; 415 416 tsc: tsc@02040000 { 417 compatible = "fsl,imx6ul-tsc"; 418 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; 419 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clks IMX6UL_CLK_IPG>, 422 <&clks IMX6UL_CLK_ADC2>; 423 clock-names = "tsc", "adc"; 424 status = "disabled"; 425 }; 426 427 pwm1: pwm@02080000 { 428 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 429 reg = <0x02080000 0x4000>; 430 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&clks IMX6UL_CLK_PWM1>, 432 <&clks IMX6UL_CLK_PWM1>; 433 clock-names = "ipg", "per"; 434 #pwm-cells = <2>; 435 }; 436 437 pwm2: pwm@02084000 { 438 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 439 reg = <0x02084000 0x4000>; 440 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clks IMX6UL_CLK_DUMMY>, 442 <&clks IMX6UL_CLK_DUMMY>; 443 clock-names = "ipg", "per"; 444 #pwm-cells = <2>; 445 }; 446 447 pwm3: pwm@02088000 { 448 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 449 reg = <0x02088000 0x4000>; 450 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&clks IMX6UL_CLK_PWM3>, 452 <&clks IMX6UL_CLK_PWM3>; 453 clock-names = "ipg", "per"; 454 #pwm-cells = <2>; 455 }; 456 457 pwm4: pwm@0208c000 { 458 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 459 reg = <0x0208c000 0x4000>; 460 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&clks IMX6UL_CLK_DUMMY>, 462 <&clks IMX6UL_CLK_DUMMY>; 463 clock-names = "ipg", "per"; 464 #pwm-cells = <2>; 465 }; 466 467 flexcan1: can@02090000 { 468 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 469 reg = <0x02090000 0x4000>; 470 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&clks IMX6UL_CLK_CAN1_IPG>, 472 <&clks IMX6UL_CLK_CAN1_SERIAL>; 473 clock-names = "ipg", "per"; 474 stop-mode = <&gpr 0x10 1 0x10 17>; 475 status = "disabled"; 476 }; 477 478 flexcan2: can@02094000 { 479 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 480 reg = <0x02094000 0x4000>; 481 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&clks IMX6UL_CLK_CAN2_IPG>, 483 <&clks IMX6UL_CLK_CAN2_SERIAL>; 484 clock-names = "ipg", "per"; 485 stop-mode = <&gpr 0x10 2 0x10 18>; 486 status = "disabled"; 487 }; 488 489 gpt1: gpt@02098000 { 490 compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt"; 491 reg = <0x02098000 0x4000>; 492 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&clks IMX6UL_CLK_GPT1_BUS>, 494 <&clks IMX6UL_CLK_GPT1_SERIAL>; 495 clock-names = "ipg", "per"; 496 }; 497 498 gpio1: gpio@0209c000 { 499 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 500 reg = <0x0209c000 0x4000>; 501 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 503 gpio-controller; 504 #gpio-cells = <2>; 505 interrupt-controller; 506 #interrupt-cells = <2>; 507 }; 508 509 gpio2: gpio@020a0000 { 510 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 511 reg = <0x020a0000 0x4000>; 512 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 514 gpio-controller; 515 #gpio-cells = <2>; 516 interrupt-controller; 517 #interrupt-cells = <2>; 518 }; 519 520 gpio3: gpio@020a4000 { 521 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 522 reg = <0x020a4000 0x4000>; 523 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 525 gpio-controller; 526 #gpio-cells = <2>; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 }; 530 531 gpio4: gpio@020a8000 { 532 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 533 reg = <0x020a8000 0x4000>; 534 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 536 gpio-controller; 537 #gpio-cells = <2>; 538 interrupt-controller; 539 #interrupt-cells = <2>; 540 }; 541 542 gpio5: gpio@020ac000 { 543 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 544 reg = <0x020ac000 0x4000>; 545 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 547 gpio-controller; 548 #gpio-cells = <2>; 549 interrupt-controller; 550 #interrupt-cells = <2>; 551 }; 552 553 snvslp: snvs@020b0000 { 554 compatible = "fsl,imx6ul-snvs"; 555 reg = <0x020b0000 0x4000>; 556 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 557 }; 558 559 fec2: ethernet@020b4000 { 560 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 561 reg = <0x020b4000 0x4000>; 562 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&clks IMX6UL_CLK_ENET>, 565 <&clks IMX6UL_CLK_ENET_AHB>, 566 <&clks IMX6UL_CLK_ENET_PTP>, 567 <&clks IMX6UL_CLK_ENET2_REF_125M>, 568 <&clks IMX6UL_CLK_ENET2_REF_125M>; 569 clock-names = "ipg", "ahb", "ptp", 570 "enet_clk_ref", "enet_out"; 571 stop-mode = <&gpr 0x10 4>; 572 fsl,num-tx-queues=<1>; 573 fsl,num-rx-queues=<1>; 574 fsl,magic-packet; 575 fsl,wakeup_irq = <0>; 576 status = "disabled"; 577 }; 578 579 kpp: kpp@020b8000 { 580 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; 581 reg = <0x020b8000 0x4000>; 582 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&clks IMX6UL_CLK_DUMMY>; 584 status = "disabled"; 585 }; 586 587 wdog1: wdog@020bc000 { 588 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 589 reg = <0x020bc000 0x4000>; 590 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&clks IMX6UL_CLK_WDOG1>; 592 }; 593 594 wdog2: wdog@020c0000 { 595 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 596 reg = <0x020c0000 0x4000>; 597 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&clks IMX6UL_CLK_WDOG2>; 599 status = "disabled"; 600 }; 601 602 clks: ccm@020c4000 { 603 compatible = "fsl,imx6ul-ccm"; 604 reg = <0x020c4000 0x4000>; 605 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 607 #clock-cells = <1>; 608 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 609 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 610 }; 611 612 anatop: anatop@020c8000 { 613 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", 614 "syscon", "simple-bus"; 615 reg = <0x020c8000 0x1000>; 616 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 619 620 reg_3p0: regulator-3p0@120 { 621 compatible = "fsl,anatop-regulator"; 622 regulator-name = "vdd3p0"; 623 regulator-min-microvolt = <2625000>; 624 regulator-max-microvolt = <3400000>; 625 anatop-reg-offset = <0x120>; 626 anatop-vol-bit-shift = <8>; 627 anatop-vol-bit-width = <5>; 628 anatop-min-bit-val = <0>; 629 anatop-min-voltage = <2625000>; 630 anatop-max-voltage = <3400000>; 631 anatop-enable-bit = <0>; 632 }; 633 634 reg_arm: regulator-vddcore@140 { 635 compatible = "fsl,anatop-regulator"; 636 regulator-name = "cpu"; 637 regulator-min-microvolt = <725000>; 638 regulator-max-microvolt = <1450000>; 639 regulator-always-on; 640 anatop-reg-offset = <0x140>; 641 anatop-vol-bit-shift = <0>; 642 anatop-vol-bit-width = <5>; 643 anatop-delay-reg-offset = <0x170>; 644 anatop-delay-bit-shift = <24>; 645 anatop-delay-bit-width = <2>; 646 anatop-min-bit-val = <1>; 647 anatop-min-voltage = <725000>; 648 anatop-max-voltage = <1450000>; 649 }; 650 651 reg_soc: regulator-vddsoc@140 { 652 compatible = "fsl,anatop-regulator"; 653 regulator-name = "vddsoc"; 654 regulator-min-microvolt = <725000>; 655 regulator-max-microvolt = <1450000>; 656 regulator-always-on; 657 anatop-reg-offset = <0x140>; 658 anatop-vol-bit-shift = <18>; 659 anatop-vol-bit-width = <5>; 660 anatop-delay-reg-offset = <0x170>; 661 anatop-delay-bit-shift = <28>; 662 anatop-delay-bit-width = <2>; 663 anatop-min-bit-val = <1>; 664 anatop-min-voltage = <725000>; 665 anatop-max-voltage = <1450000>; 666 }; 667 }; 668 669 usbphy1: usbphy@020c9000 { 670 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 671 reg = <0x020c9000 0x1000>; 672 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&clks IMX6UL_CLK_USBPHY1>; 674 phy-3p0-supply = <®_3p0>; 675 fsl,anatop = <&anatop>; 676 }; 677 678 usbphy2: usbphy@020ca000 { 679 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 680 reg = <0x020ca000 0x1000>; 681 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&clks IMX6UL_CLK_USBPHY2>; 683 phy-3p0-supply = <®_3p0>; 684 fsl,anatop = <&anatop>; 685 }; 686 687 tempmon: tempmon { 688 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; 689 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 690 fsl,tempmon = <&anatop>; 691 fsl,tempmon-data = <&ocotp>; 692 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; 693 }; 694 695 snvs: snvs@020cc000 { 696 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 697 reg = <0x020cc000 0x4000>; 698 699 snvs_rtc: snvs-rtc-lp { 700 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 701 regmap = <&snvs>; 702 offset = <0x34>; 703 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 704 }; 705 706 snvs_poweroff: snvs-poweroff { 707 compatible = "syscon-poweroff"; 708 regmap = <&snvs>; 709 offset = <0x38>; 710 mask = <0x61>; 711 }; 712 713 snvs_pwrkey: snvs-powerkey { 714 compatible = "fsl,sec-v4.0-pwrkey"; 715 regmap = <&snvs>; 716 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 717 linux,keycode = <KEY_POWER>; 718 wakeup; 719 }; 720 }; 721 722 epit1: epit@020d0000 { 723 reg = <0x020d0000 0x4000>; 724 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 725 }; 726 727 epit2: epit@020d4000 { 728 reg = <0x020d4000 0x4000>; 729 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 730 }; 731 732 src: src@020d8000 { 733 compatible = "fsl,imx6ul-src", "fsl,imx51-src"; 734 reg = <0x020d8000 0x4000>; 735 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 737 #reset-cells = <1>; 738 }; 739 740 gpc: gpc@020dc000 { 741 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; 742 reg = <0x020dc000 0x4000>; 743 interrupt-controller; 744 #interrupt-cells = <3>; 745 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 746 interrupt-parent = <&intc>; 747 fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>; 748 }; 749 750 iomuxc: iomuxc@020e0000 { 751 compatible = "fsl,imx6ul-iomuxc"; 752 reg = <0x020e0000 0x4000>; 753 }; 754 755 gpr: iomuxc-gpr@020e4000 { 756 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon"; 757 reg = <0x020e4000 0x4000>; 758 }; 759 760 mqs: mqs { 761 compatible = "fsl,imx6sx-mqs"; 762 gpr = <&gpr>; 763 status = "disabled"; 764 }; 765 766 gpt2: gpt@020e8000 { 767 compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt"; 768 reg = <0x020e8000 0x4000>; 769 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&clks IMX6UL_CLK_DUMMY>, 771 <&clks IMX6UL_CLK_DUMMY>; 772 clock-names = "ipg", "per"; 773 }; 774 775 sdma: sdma@020ec000 { 776 compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma"; 777 reg = <0x020ec000 0x4000>; 778 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&clks IMX6UL_CLK_SDMA>, 780 <&clks IMX6UL_CLK_SDMA>; 781 clock-names = "ipg", "ahb"; 782 #dma-cells = <3>; 783 iram = <&ocram>; 784 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 785 }; 786 787 pwm5: pwm@020f0000 { 788 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 789 reg = <0x020f0000 0x4000>; 790 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&clks IMX6UL_CLK_DUMMY>, 792 <&clks IMX6UL_CLK_DUMMY>; 793 clock-names = "ipg", "per"; 794 #pwm-cells = <2>; 795 }; 796 797 pwm6: pwm@020f4000 { 798 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 799 reg = <0x020f4000 0x4000>; 800 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&clks IMX6UL_CLK_DUMMY>, 802 <&clks IMX6UL_CLK_DUMMY>; 803 clock-names = "ipg", "per"; 804 #pwm-cells = <2>; 805 }; 806 807 pwm7: pwm@020f8000 { 808 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 809 reg = <0x020f8000 0x4000>; 810 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&clks IMX6UL_CLK_DUMMY>, 812 <&clks IMX6UL_CLK_DUMMY>; 813 clock-names = "ipg", "per"; 814 #pwm-cells = <2>; 815 }; 816 817 pwm8: pwm@020fc000 { 818 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 819 reg = <0x020fc000 0x4000>; 820 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&clks IMX6UL_CLK_DUMMY>, 822 <&clks IMX6UL_CLK_DUMMY>; 823 clock-names = "ipg", "per"; 824 #pwm-cells = <2>; 825 }; 826 }; 827 828 aips2: aips-bus@02100000 { 829 compatible = "fsl,aips-bus", "simple-bus"; 830 #address-cells = <1>; 831 #size-cells = <1>; 832 reg = <0x02100000 0x100000>; 833 ranges; 834 835 usbotg1: usb@02184000 { 836 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 837 reg = <0x02184000 0x200>; 838 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&clks IMX6UL_CLK_USBOH3>; 840 fsl,usbphy = <&usbphy1>; 841 fsl,usbmisc = <&usbmisc 0>; 842 fsl,anatop = <&anatop>; 843 ahb-burst-config = <0x0>; 844 tx-burst-size-dword = <0x10>; 845 rx-burst-size-dword = <0x10>; 846 status = "disabled"; 847 }; 848 849 usbotg2: usb@02184200 { 850 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 851 reg = <0x02184200 0x200>; 852 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&clks IMX6UL_CLK_USBOH3>; 854 fsl,usbphy = <&usbphy2>; 855 fsl,usbmisc = <&usbmisc 1>; 856 ahb-burst-config = <0x0>; 857 tx-burst-size-dword = <0x10>; 858 rx-burst-size-dword = <0x10>; 859 status = "disabled"; 860 }; 861 862 usbmisc: usbmisc@02184800 { 863 #index-cells = <1>; 864 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; 865 reg = <0x02184800 0x200>; 866 }; 867 868 fec1: ethernet@02188000 { 869 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 870 reg = <0x02188000 0x4000>; 871 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&clks IMX6UL_CLK_ENET>, 874 <&clks IMX6UL_CLK_ENET_AHB>, 875 <&clks IMX6UL_CLK_ENET_PTP>, 876 <&clks IMX6UL_CLK_ENET_REF>, 877 <&clks IMX6UL_CLK_ENET_REF>; 878 clock-names = "ipg", "ahb", "ptp", 879 "enet_clk_ref", "enet_out"; 880 stop-mode = <&gpr 0x10 3>; 881 fsl,num-tx-queues=<1>; 882 fsl,num-rx-queues=<1>; 883 fsl,magic-packet; 884 fsl,wakeup_irq = <0>; 885 status = "disabled"; 886 }; 887 888 usdhc1: usdhc@02190000 { 889 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 890 reg = <0x02190000 0x4000>; 891 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&clks IMX6UL_CLK_USDHC1>, 893 <&clks IMX6UL_CLK_USDHC1>, 894 <&clks IMX6UL_CLK_USDHC1>; 895 clock-names = "ipg", "ahb", "per"; 896 bus-width = <4>; 897 fsl,tuning-step= <2>; 898 status = "disabled"; 899 }; 900 901 usdhc2: usdhc@02194000 { 902 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 903 reg = <0x02194000 0x4000>; 904 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&clks IMX6UL_CLK_USDHC2>, 906 <&clks IMX6UL_CLK_USDHC2>, 907 <&clks IMX6UL_CLK_USDHC2>; 908 clock-names = "ipg", "ahb", "per"; 909 bus-width = <4>; 910 fsl,tuning-step= <2>; 911 status = "disabled"; 912 }; 913 914 adc1: adc@02198000 { 915 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; 916 reg = <0x02198000 0x4000>; 917 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&clks IMX6UL_CLK_ADC1>; 919 num-channels = <2>; 920 clock-names = "adc"; 921 status = "disabled"; 922 }; 923 924 i2c1: i2c@021a0000 { 925 #address-cells = <1>; 926 #size-cells = <0>; 927 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 928 reg = <0x021a0000 0x4000>; 929 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&clks IMX6UL_CLK_I2C1>; 931 status = "disabled"; 932 }; 933 934 i2c2: i2c@021a4000 { 935 #address-cells = <1>; 936 #size-cells = <0>; 937 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 938 reg = <0x021a4000 0x4000>; 939 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&clks IMX6UL_CLK_I2C2>; 941 status = "disabled"; 942 }; 943 944 i2c3: i2c@021a8000 { 945 #address-cells = <1>; 946 #size-cells = <0>; 947 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 948 reg = <0x021a8000 0x4000>; 949 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&clks IMX6UL_CLK_I2C3>; 951 status = "disabled"; 952 }; 953 954 romcp@021ac000 { 955 compatible = "fsl,imx6ul-romcp", "syscon"; 956 reg = <0x021ac000 0x4000>; 957 }; 958 959 mmdc: mmdc@021b0000 { 960 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; 961 reg = <0x021b0000 0x4000>; 962 }; 963 964 weim: weim@021b8000 { 965 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; 966 reg = <0x021b8000 0x4000>; 967 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&clks IMX6UL_CLK_DUMMY>; 969 }; 970 971 ocotp: ocotp-ctrl@021bc000 { 972 compatible = "fsl,imx6ull-ocotp", "syscon"; 973 reg = <0x021bc000 0x4000>; 974 clocks = <&clks IMX6UL_CLK_OCOTP>; 975 }; 976 977 csu: csu@021c0000 { 978 compatible = "fsl,imx6ul-csu"; 979 reg = <0x021c0000 0x4000>; 980 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 981 status = "disabled"; 982 }; 983 984 csi: csi@021c4000 { 985 compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi"; 986 reg = <0x021c4000 0x4000>; 987 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&clks IMX6UL_CLK_DUMMY>, 989 <&clks IMX6UL_CLK_CSI>, 990 <&clks IMX6UL_CLK_DUMMY>; 991 clock-names = "disp-axi", "csi_mclk", "disp_dcic"; 992 status = "disabled"; 993 }; 994 995 lcdif: lcdif@021c8000 { 996 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; 997 reg = <0x021c8000 0x4000>; 998 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, 1000 <&clks IMX6UL_CLK_LCDIF_APB>, 1001 <&clks IMX6UL_CLK_DUMMY>; 1002 clock-names = "pix", "axi", "disp_axi"; 1003 status = "disabled"; 1004 }; 1005 1006 pxp: pxp@021cc000 { 1007 compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; 1008 reg = <0x021cc000 0x4000>; 1009 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>; 1012 clock-names = "pxp_ipg", "pxp_axi"; 1013 status = "disabled"; 1014 }; 1015 1016 qspi: qspi@021e0000 { 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 compatible = "fsl,imx6ull-qspi", "fsl,imx6ul-qspi"; 1020 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1021 reg-names = "QuadSPI", "QuadSPI-memory"; 1022 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&clks IMX6UL_CLK_QSPI>, 1024 <&clks IMX6UL_CLK_QSPI>; 1025 clock-names = "qspi_en", "qspi"; 1026 status = "disabled"; 1027 }; 1028 1029 wdog3: wdog@021e4000 { 1030 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 1031 reg = <0x021e4000 0x4000>; 1032 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&clks IMX6UL_CLK_WDOG3>; 1034 status = "disabled"; 1035 }; 1036 1037 uart2: serial@021e8000 { 1038 compatible = "fsl,imx6ul-uart", 1039 "fsl,imx6q-uart", "fsl,imx21-uart"; 1040 reg = <0x021e8000 0x4000>; 1041 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&clks IMX6UL_CLK_UART2_IPG>, 1043 <&clks IMX6UL_CLK_UART2_SERIAL>; 1044 clock-names = "ipg", "per"; 1045 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1046 dma-names = "rx", "tx"; 1047 status = "disabled"; 1048 }; 1049 1050 uart3: serial@021ec000 { 1051 compatible = "fsl,imx6ul-uart", 1052 "fsl,imx6q-uart", "fsl,imx21-uart"; 1053 reg = <0x021ec000 0x4000>; 1054 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&clks IMX6UL_CLK_UART3_IPG>, 1056 <&clks IMX6UL_CLK_UART3_SERIAL>; 1057 clock-names = "ipg", "per"; 1058 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1059 dma-names = "rx", "tx"; 1060 status = "disabled"; 1061 }; 1062 1063 uart4: serial@021f0000 { 1064 compatible = "fsl,imx6ul-uart", 1065 "fsl,imx6q-uart", "fsl,imx21-uart"; 1066 reg = <0x021f0000 0x4000>; 1067 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&clks IMX6UL_CLK_UART4_IPG>, 1069 <&clks IMX6UL_CLK_UART4_SERIAL>; 1070 clock-names = "ipg", "per"; 1071 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1072 dma-names = "rx", "tx"; 1073 status = "disabled"; 1074 }; 1075 1076 uart5: serial@021f4000 { 1077 compatible = "fsl,imx6ul-uart", 1078 "fsl,imx6q-uart", "fsl,imx21-uart"; 1079 reg = <0x021f4000 0x4000>; 1080 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&clks IMX6UL_CLK_UART5_IPG>, 1082 <&clks IMX6UL_CLK_UART5_SERIAL>; 1083 clock-names = "ipg", "per"; 1084 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1085 dma-names = "rx", "tx"; 1086 status = "disabled"; 1087 }; 1088 1089 i2c4: i2c@021f8000 { 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 1093 reg = <0x021f8000 0x4000>; 1094 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&clks IMX6UL_CLK_I2C4>; 1096 status = "disabled"; 1097 }; 1098 1099 uart6: serial@021fc000 { 1100 compatible = "fsl,imx6ul-uart", 1101 "fsl,imx6q-uart", "fsl,imx21-uart"; 1102 reg = <0x021fc000 0x4000>; 1103 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&clks IMX6UL_CLK_UART6_IPG>, 1105 <&clks IMX6UL_CLK_UART6_SERIAL>; 1106 clock-names = "ipg", "per"; 1107 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; 1108 dma-names = "rx", "tx"; 1109 status = "disabled"; 1110 }; 1111 }; 1112 1113 aips3: aips-bus@02200000 { 1114 compatible = "fsl,aips-bus", "simple-bus"; 1115 #address-cells = <1>; 1116 #size-cells = <1>; 1117 reg = <0x02200000 0x100000>; 1118 ranges; 1119 1120 dcp: dcp@02280000 { 1121 reg = <0x02280000 0x4000>; 1122 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1125 /*clocks = <&clks IMX6UL_CLK_DCP>;*/ 1126 clock-names = "dcp"; 1127 status = "disabled"; 1128 }; 1129 1130 rngb: rngb@02284000 { 1131 reg = <0x02284000 0x4000>; 1132 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1133 }; 1134 1135 uart8: serial@02288000 { 1136 compatible = "fsl,imx6ul-uart", 1137 "fsl,imx6q-uart", "fsl,imx21-uart"; 1138 reg = <0x02288000 0x4000>; 1139 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&clks IMX6UL_CLK_UART8_IPG>, 1141 <&clks IMX6UL_CLK_UART8_SERIAL>; 1142 clock-names = "ipg", "per"; 1143 dmas = <&sdma 45 4 0>, <&sdma 46 4 0>; 1144 dma-names = "rx", "tx"; 1145 status = "disabled"; 1146 }; 1147 1148 epdc: epdc@0228c000 { 1149 compatible = "fsl,imx7d-epdc"; 1150 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1151 reg = <0x0228c000 0x4000>; 1152 clocks = <&clks IMX6UL_CLK_EPDC_ACLK>, 1153 <&clks IMX6UL_CLK_EPDC_PIX>; 1154 clock-names = "epdc_axi", "epdc_pix"; 1155 /* Need to fix epdc-ram */ 1156 /* epdc-ram = <&gpr 0x4 30>; */ 1157 status = "disabled"; 1158 }; 1159 1160 iomuxc_snvs: iomuxc-snvs@02290000 { 1161 compatible = "fsl,imx6ull-iomuxc-snvs"; 1162 reg = <0x02290000 0x10000>; 1163 }; 1164 1165 snvs_gpr: snvs-gpr@0x02294000 { 1166 compatible = "fsl, imx6ull-snvs-gpr"; 1167 reg = <0x02294000 0x10000>; 1168 }; 1169 }; 1170 }; 1171 }; 1172
