1 /* 2 * Device Tree Source for OMAP3 SoC 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/interrupt-controller/irq.h> 13 #include <dt-bindings/pinctrl/omap.h> 14 15 / { 16 compatible = "ti,omap3430", "ti,omap3"; 17 interrupt-parent = <&intc>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 chosen { }; 21 22 aliases { 23 i2c0 = &i2c1; 24 i2c1 = &i2c2; 25 i2c2 = &i2c3; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu@0 { 36 compatible = "arm,cortex-a8"; 37 device_type = "cpu"; 38 reg = <0x0>; 39 40 clocks = <&dpll1_ck>; 41 clock-names = "cpu"; 42 43 clock-latency = <300000>; /* From omap-cpufreq driver */ 44 }; 45 }; 46 47 pmu@54000000 { 48 compatible = "arm,cortex-a8-pmu"; 49 reg = <0x54000000 0x800000>; 50 interrupts = <3>; 51 ti,hwmods = "debugss"; 52 }; 53 54 /* 55 * The soc node represents the soc top level view. It is used for IPs 56 * that are not memory mapped in the MPU view or for the MPU itself. 57 */ 58 soc { 59 compatible = "ti,omap-infra"; 60 mpu { 61 compatible = "ti,omap3-mpu"; 62 ti,hwmods = "mpu"; 63 }; 64 65 iva: iva { 66 compatible = "ti,iva2.2"; 67 ti,hwmods = "iva"; 68 69 dsp { 70 compatible = "ti,omap3-c64"; 71 }; 72 }; 73 }; 74 75 /* 76 * XXX: Use a flat representation of the OMAP3 interconnect. 77 * The real OMAP interconnect network is quite complex. 78 * Since it will not bring real advantage to represent that in DT for 79 * the moment, just use a fake OCP bus entry to represent the whole bus 80 * hierarchy. 81 */ 82 ocp@68000000 { 83 compatible = "ti,omap3-l3-smx", "simple-bus"; 84 reg = <0x68000000 0x10000>; 85 interrupts = <9 10>; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges; 89 ti,hwmods = "l3_main"; 90 91 l4_core: l4@48000000 { 92 compatible = "ti,omap3-l4-core", "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 ranges = <0 0x48000000 0x1000000>; 96 97 scm: scm@2000 { 98 compatible = "ti,omap3-scm", "simple-bus"; 99 reg = <0x2000 0x2000>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0 0x2000 0x2000>; 103 104 omap3_pmx_core: pinmux@30 { 105 compatible = "ti,omap3-padconf", 106 "pinctrl-single"; 107 reg = <0x30 0x238>; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 #pinctrl-cells = <1>; 111 #interrupt-cells = <1>; 112 interrupt-controller; 113 pinctrl-single,register-width = <16>; 114 pinctrl-single,function-mask = <0xff1f>; 115 }; 116 117 scm_conf: scm_conf@270 { 118 compatible = "syscon", "simple-bus"; 119 reg = <0x270 0x330>; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges = <0 0x270 0x330>; 123 124 pbias_regulator: pbias_regulator@2b0 { 125 compatible = "ti,pbias-omap3", "ti,pbias-omap"; 126 reg = <0x2b0 0x4>; 127 syscon = <&scm_conf>; 128 pbias_mmc_reg: pbias_mmc_omap2430 { 129 regulator-name = "pbias_mmc_omap2430"; 130 regulator-min-microvolt = <1800000>; 131 regulator-max-microvolt = <3000000>; 132 }; 133 }; 134 135 scm_clocks: clocks { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 }; 139 }; 140 141 scm_clockdomains: clockdomains { 142 }; 143 144 omap3_pmx_wkup: pinmux@a00 { 145 compatible = "ti,omap3-padconf", 146 "pinctrl-single"; 147 reg = <0xa00 0x5c>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 #pinctrl-cells = <1>; 151 #interrupt-cells = <1>; 152 interrupt-controller; 153 pinctrl-single,register-width = <16>; 154 pinctrl-single,function-mask = <0xff1f>; 155 }; 156 }; 157 }; 158 159 aes: aes@480c5000 { 160 compatible = "ti,omap3-aes"; 161 ti,hwmods = "aes"; 162 reg = <0x480c5000 0x50>; 163 interrupts = <0>; 164 dmas = <&sdma 65 &sdma 66>; 165 dma-names = "tx", "rx"; 166 }; 167 168 prm: prm@48306000 { 169 compatible = "ti,omap3-prm"; 170 reg = <0x48306000 0x4000>; 171 interrupts = <11>; 172 173 prm_clocks: clocks { 174 #address-cells = <1>; 175 #size-cells = <0>; 176 }; 177 178 prm_clockdomains: clockdomains { 179 }; 180 }; 181 182 cm: cm@48004000 { 183 compatible = "ti,omap3-cm"; 184 reg = <0x48004000 0x4000>; 185 186 cm_clocks: clocks { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 }; 190 191 cm_clockdomains: clockdomains { 192 }; 193 }; 194 195 counter32k: counter@48320000 { 196 compatible = "ti,omap-counter32k"; 197 reg = <0x48320000 0x20>; 198 ti,hwmods = "counter_32k"; 199 }; 200 201 intc: interrupt-controller@48200000 { 202 compatible = "ti,omap3-intc"; 203 interrupt-controller; 204 #interrupt-cells = <1>; 205 reg = <0x48200000 0x1000>; 206 }; 207 208 sdma: dma-controller@48056000 { 209 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; 210 reg = <0x48056000 0x1000>; 211 interrupts = <12>, 212 <13>, 213 <14>, 214 <15>; 215 #dma-cells = <1>; 216 dma-channels = <32>; 217 dma-requests = <96>; 218 }; 219 220 gpio1: gpio@48310000 { 221 compatible = "ti,omap3-gpio"; 222 reg = <0x48310000 0x200>; 223 interrupts = <29>; 224 ti,hwmods = "gpio1"; 225 ti,gpio-always-on; 226 gpio-controller; 227 #gpio-cells = <2>; 228 interrupt-controller; 229 #interrupt-cells = <2>; 230 }; 231 232 gpio2: gpio@49050000 { 233 compatible = "ti,omap3-gpio"; 234 reg = <0x49050000 0x200>; 235 interrupts = <30>; 236 ti,hwmods = "gpio2"; 237 gpio-controller; 238 #gpio-cells = <2>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 }; 242 243 gpio3: gpio@49052000 { 244 compatible = "ti,omap3-gpio"; 245 reg = <0x49052000 0x200>; 246 interrupts = <31>; 247 ti,hwmods = "gpio3"; 248 gpio-controller; 249 #gpio-cells = <2>; 250 interrupt-controller; 251 #interrupt-cells = <2>; 252 }; 253 254 gpio4: gpio@49054000 { 255 compatible = "ti,omap3-gpio"; 256 reg = <0x49054000 0x200>; 257 interrupts = <32>; 258 ti,hwmods = "gpio4"; 259 gpio-controller; 260 #gpio-cells = <2>; 261 interrupt-controller; 262 #interrupt-cells = <2>; 263 }; 264 265 gpio5: gpio@49056000 { 266 compatible = "ti,omap3-gpio"; 267 reg = <0x49056000 0x200>; 268 interrupts = <33>; 269 ti,hwmods = "gpio5"; 270 gpio-controller; 271 #gpio-cells = <2>; 272 interrupt-controller; 273 #interrupt-cells = <2>; 274 }; 275 276 gpio6: gpio@49058000 { 277 compatible = "ti,omap3-gpio"; 278 reg = <0x49058000 0x200>; 279 interrupts = <34>; 280 ti,hwmods = "gpio6"; 281 gpio-controller; 282 #gpio-cells = <2>; 283 interrupt-controller; 284 #interrupt-cells = <2>; 285 }; 286 287 uart1: serial@4806a000 { 288 compatible = "ti,omap3-uart"; 289 reg = <0x4806a000 0x2000>; 290 reg-shift = <2>; 291 interrupts-extended = <&intc 72>; 292 dmas = <&sdma 49 &sdma 50>; 293 dma-names = "tx", "rx"; 294 ti,hwmods = "uart1"; 295 clock-frequency = <48000000>; 296 }; 297 298 uart2: serial@4806c000 { 299 compatible = "ti,omap3-uart"; 300 reg = <0x4806c000 0x400>; 301 reg-shift = <2>; 302 interrupts-extended = <&intc 73>; 303 dmas = <&sdma 51 &sdma 52>; 304 dma-names = "tx", "rx"; 305 ti,hwmods = "uart2"; 306 clock-frequency = <48000000>; 307 }; 308 309 uart3: serial@49020000 { 310 compatible = "ti,omap3-uart"; 311 reg = <0x49020000 0x400>; 312 reg-shift = <2>; 313 interrupts-extended = <&intc 74>; 314 dmas = <&sdma 53 &sdma 54>; 315 dma-names = "tx", "rx"; 316 ti,hwmods = "uart3"; 317 clock-frequency = <48000000>; 318 }; 319 320 i2c1: i2c@48070000 { 321 compatible = "ti,omap3-i2c"; 322 reg = <0x48070000 0x80>; 323 interrupts = <56>; 324 dmas = <&sdma 27 &sdma 28>; 325 dma-names = "tx", "rx"; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 ti,hwmods = "i2c1"; 329 }; 330 331 i2c2: i2c@48072000 { 332 compatible = "ti,omap3-i2c"; 333 reg = <0x48072000 0x80>; 334 interrupts = <57>; 335 dmas = <&sdma 29 &sdma 30>; 336 dma-names = "tx", "rx"; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 ti,hwmods = "i2c2"; 340 }; 341 342 i2c3: i2c@48060000 { 343 compatible = "ti,omap3-i2c"; 344 reg = <0x48060000 0x80>; 345 interrupts = <61>; 346 dmas = <&sdma 25 &sdma 26>; 347 dma-names = "tx", "rx"; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 ti,hwmods = "i2c3"; 351 }; 352 353 mailbox: mailbox@48094000 { 354 compatible = "ti,omap3-mailbox"; 355 ti,hwmods = "mailbox"; 356 reg = <0x48094000 0x200>; 357 interrupts = <26>; 358 #mbox-cells = <1>; 359 ti,mbox-num-users = <2>; 360 ti,mbox-num-fifos = <2>; 361 mbox_dsp: dsp { 362 ti,mbox-tx = <0 0 0>; 363 ti,mbox-rx = <1 0 0>; 364 }; 365 }; 366 367 mcspi1: spi@48098000 { 368 compatible = "ti,omap2-mcspi"; 369 reg = <0x48098000 0x100>; 370 interrupts = <65>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 ti,hwmods = "mcspi1"; 374 ti,spi-num-cs = <4>; 375 dmas = <&sdma 35>, 376 <&sdma 36>, 377 <&sdma 37>, 378 <&sdma 38>, 379 <&sdma 39>, 380 <&sdma 40>, 381 <&sdma 41>, 382 <&sdma 42>; 383 dma-names = "tx0", "rx0", "tx1", "rx1", 384 "tx2", "rx2", "tx3", "rx3"; 385 }; 386 387 mcspi2: spi@4809a000 { 388 compatible = "ti,omap2-mcspi"; 389 reg = <0x4809a000 0x100>; 390 interrupts = <66>; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 ti,hwmods = "mcspi2"; 394 ti,spi-num-cs = <2>; 395 dmas = <&sdma 43>, 396 <&sdma 44>, 397 <&sdma 45>, 398 <&sdma 46>; 399 dma-names = "tx0", "rx0", "tx1", "rx1"; 400 }; 401 402 mcspi3: spi@480b8000 { 403 compatible = "ti,omap2-mcspi"; 404 reg = <0x480b8000 0x100>; 405 interrupts = <91>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 ti,hwmods = "mcspi3"; 409 ti,spi-num-cs = <2>; 410 dmas = <&sdma 15>, 411 <&sdma 16>, 412 <&sdma 23>, 413 <&sdma 24>; 414 dma-names = "tx0", "rx0", "tx1", "rx1"; 415 }; 416 417 mcspi4: spi@480ba000 { 418 compatible = "ti,omap2-mcspi"; 419 reg = <0x480ba000 0x100>; 420 interrupts = <48>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 ti,hwmods = "mcspi4"; 424 ti,spi-num-cs = <1>; 425 dmas = <&sdma 70>, <&sdma 71>; 426 dma-names = "tx0", "rx0"; 427 }; 428 429 hdqw1w: 1w@480b2000 { 430 compatible = "ti,omap3-1w"; 431 reg = <0x480b2000 0x1000>; 432 interrupts = <58>; 433 ti,hwmods = "hdq1w"; 434 }; 435 436 mmc1: mmc@4809c000 { 437 compatible = "ti,omap3-hsmmc"; 438 reg = <0x4809c000 0x200>; 439 interrupts = <83>; 440 ti,hwmods = "mmc1"; 441 ti,dual-volt; 442 dmas = <&sdma 61>, <&sdma 62>; 443 dma-names = "tx", "rx"; 444 pbias-supply = <&pbias_mmc_reg>; 445 }; 446 447 mmc2: mmc@480b4000 { 448 compatible = "ti,omap3-hsmmc"; 449 reg = <0x480b4000 0x200>; 450 interrupts = <86>; 451 ti,hwmods = "mmc2"; 452 dmas = <&sdma 47>, <&sdma 48>; 453 dma-names = "tx", "rx"; 454 }; 455 456 mmc3: mmc@480ad000 { 457 compatible = "ti,omap3-hsmmc"; 458 reg = <0x480ad000 0x200>; 459 interrupts = <94>; 460 ti,hwmods = "mmc3"; 461 dmas = <&sdma 77>, <&sdma 78>; 462 dma-names = "tx", "rx"; 463 }; 464 465 mmu_isp: mmu@480bd400 { 466 #iommu-cells = <0>; 467 compatible = "ti,omap2-iommu"; 468 reg = <0x480bd400 0x80>; 469 interrupts = <24>; 470 ti,hwmods = "mmu_isp"; 471 ti,#tlb-entries = <8>; 472 }; 473 474 mmu_iva: mmu@5d000000 { 475 #iommu-cells = <0>; 476 compatible = "ti,omap2-iommu"; 477 reg = <0x5d000000 0x80>; 478 interrupts = <28>; 479 ti,hwmods = "mmu_iva"; 480 status = "disabled"; 481 }; 482 483 wdt2: wdt@48314000 { 484 compatible = "ti,omap3-wdt"; 485 reg = <0x48314000 0x80>; 486 ti,hwmods = "wd_timer2"; 487 }; 488 489 mcbsp1: mcbsp@48074000 { 490 compatible = "ti,omap3-mcbsp"; 491 reg = <0x48074000 0xff>; 492 reg-names = "mpu"; 493 interrupts = <16>, /* OCP compliant interrupt */ 494 <59>, /* TX interrupt */ 495 <60>; /* RX interrupt */ 496 interrupt-names = "common", "tx", "rx"; 497 ti,buffer-size = <128>; 498 ti,hwmods = "mcbsp1"; 499 dmas = <&sdma 31>, 500 <&sdma 32>; 501 dma-names = "tx", "rx"; 502 clocks = <&mcbsp1_fck>; 503 clock-names = "fck"; 504 status = "disabled"; 505 }; 506 507 mcbsp2: mcbsp@49022000 { 508 compatible = "ti,omap3-mcbsp"; 509 reg = <0x49022000 0xff>, 510 <0x49028000 0xff>; 511 reg-names = "mpu", "sidetone"; 512 interrupts = <17>, /* OCP compliant interrupt */ 513 <62>, /* TX interrupt */ 514 <63>, /* RX interrupt */ 515 <4>; /* Sidetone */ 516 interrupt-names = "common", "tx", "rx", "sidetone"; 517 ti,buffer-size = <1280>; 518 ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; 519 dmas = <&sdma 33>, 520 <&sdma 34>; 521 dma-names = "tx", "rx"; 522 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; 523 clock-names = "fck", "ick"; 524 status = "disabled"; 525 }; 526 527 mcbsp3: mcbsp@49024000 { 528 compatible = "ti,omap3-mcbsp"; 529 reg = <0x49024000 0xff>, 530 <0x4902a000 0xff>; 531 reg-names = "mpu", "sidetone"; 532 interrupts = <22>, /* OCP compliant interrupt */ 533 <89>, /* TX interrupt */ 534 <90>, /* RX interrupt */ 535 <5>; /* Sidetone */ 536 interrupt-names = "common", "tx", "rx", "sidetone"; 537 ti,buffer-size = <128>; 538 ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; 539 dmas = <&sdma 17>, 540 <&sdma 18>; 541 dma-names = "tx", "rx"; 542 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; 543 clock-names = "fck", "ick"; 544 status = "disabled"; 545 }; 546 547 mcbsp4: mcbsp@49026000 { 548 compatible = "ti,omap3-mcbsp"; 549 reg = <0x49026000 0xff>; 550 reg-names = "mpu"; 551 interrupts = <23>, /* OCP compliant interrupt */ 552 <54>, /* TX interrupt */ 553 <55>; /* RX interrupt */ 554 interrupt-names = "common", "tx", "rx"; 555 ti,buffer-size = <128>; 556 ti,hwmods = "mcbsp4"; 557 dmas = <&sdma 19>, 558 <&sdma 20>; 559 dma-names = "tx", "rx"; 560 clocks = <&mcbsp4_fck>; 561 clock-names = "fck"; 562 status = "disabled"; 563 }; 564 565 mcbsp5: mcbsp@48096000 { 566 compatible = "ti,omap3-mcbsp"; 567 reg = <0x48096000 0xff>; 568 reg-names = "mpu"; 569 interrupts = <27>, /* OCP compliant interrupt */ 570 <81>, /* TX interrupt */ 571 <82>; /* RX interrupt */ 572 interrupt-names = "common", "tx", "rx"; 573 ti,buffer-size = <128>; 574 ti,hwmods = "mcbsp5"; 575 dmas = <&sdma 21>, 576 <&sdma 22>; 577 dma-names = "tx", "rx"; 578 clocks = <&mcbsp5_fck>; 579 clock-names = "fck"; 580 status = "disabled"; 581 }; 582 583 sham: sham@480c3000 { 584 compatible = "ti,omap3-sham"; 585 ti,hwmods = "sham"; 586 reg = <0x480c3000 0x64>; 587 interrupts = <49>; 588 dmas = <&sdma 69>; 589 dma-names = "rx"; 590 }; 591 592 smartreflex_core: smartreflex@480cb000 { 593 compatible = "ti,omap3-smartreflex-core"; 594 ti,hwmods = "smartreflex_core"; 595 reg = <0x480cb000 0x400>; 596 interrupts = <19>; 597 }; 598 599 smartreflex_mpu_iva: smartreflex@480c9000 { 600 compatible = "ti,omap3-smartreflex-iva"; 601 ti,hwmods = "smartreflex_mpu_iva"; 602 reg = <0x480c9000 0x400>; 603 interrupts = <18>; 604 }; 605 606 timer1: timer@48318000 { 607 compatible = "ti,omap3430-timer"; 608 reg = <0x48318000 0x400>; 609 interrupts = <37>; 610 ti,hwmods = "timer1"; 611 ti,timer-alwon; 612 }; 613 614 timer2: timer@49032000 { 615 compatible = "ti,omap3430-timer"; 616 reg = <0x49032000 0x400>; 617 interrupts = <38>; 618 ti,hwmods = "timer2"; 619 }; 620 621 timer3: timer@49034000 { 622 compatible = "ti,omap3430-timer"; 623 reg = <0x49034000 0x400>; 624 interrupts = <39>; 625 ti,hwmods = "timer3"; 626 }; 627 628 timer4: timer@49036000 { 629 compatible = "ti,omap3430-timer"; 630 reg = <0x49036000 0x400>; 631 interrupts = <40>; 632 ti,hwmods = "timer4"; 633 }; 634 635 timer5: timer@49038000 { 636 compatible = "ti,omap3430-timer"; 637 reg = <0x49038000 0x400>; 638 interrupts = <41>; 639 ti,hwmods = "timer5"; 640 ti,timer-dsp; 641 }; 642 643 timer6: timer@4903a000 { 644 compatible = "ti,omap3430-timer"; 645 reg = <0x4903a000 0x400>; 646 interrupts = <42>; 647 ti,hwmods = "timer6"; 648 ti,timer-dsp; 649 }; 650 651 timer7: timer@4903c000 { 652 compatible = "ti,omap3430-timer"; 653 reg = <0x4903c000 0x400>; 654 interrupts = <43>; 655 ti,hwmods = "timer7"; 656 ti,timer-dsp; 657 }; 658 659 timer8: timer@4903e000 { 660 compatible = "ti,omap3430-timer"; 661 reg = <0x4903e000 0x400>; 662 interrupts = <44>; 663 ti,hwmods = "timer8"; 664 ti,timer-pwm; 665 ti,timer-dsp; 666 }; 667 668 timer9: timer@49040000 { 669 compatible = "ti,omap3430-timer"; 670 reg = <0x49040000 0x400>; 671 interrupts = <45>; 672 ti,hwmods = "timer9"; 673 ti,timer-pwm; 674 }; 675 676 timer10: timer@48086000 { 677 compatible = "ti,omap3430-timer"; 678 reg = <0x48086000 0x400>; 679 interrupts = <46>; 680 ti,hwmods = "timer10"; 681 ti,timer-pwm; 682 }; 683 684 timer11: timer@48088000 { 685 compatible = "ti,omap3430-timer"; 686 reg = <0x48088000 0x400>; 687 interrupts = <47>; 688 ti,hwmods = "timer11"; 689 ti,timer-pwm; 690 }; 691 692 timer12: timer@48304000 { 693 compatible = "ti,omap3430-timer"; 694 reg = <0x48304000 0x400>; 695 interrupts = <95>; 696 ti,hwmods = "timer12"; 697 ti,timer-alwon; 698 ti,timer-secure; 699 }; 700 701 usbhstll: usbhstll@48062000 { 702 compatible = "ti,usbhs-tll"; 703 reg = <0x48062000 0x1000>; 704 interrupts = <78>; 705 ti,hwmods = "usb_tll_hs"; 706 }; 707 708 usbhshost: usbhshost@48064000 { 709 compatible = "ti,usbhs-host"; 710 reg = <0x48064000 0x400>; 711 ti,hwmods = "usb_host_hs"; 712 #address-cells = <1>; 713 #size-cells = <1>; 714 ranges; 715 716 usbhsohci: ohci@48064400 { 717 compatible = "ti,ohci-omap3"; 718 reg = <0x48064400 0x400>; 719 interrupts = <76>; 720 }; 721 722 usbhsehci: ehci@48064800 { 723 compatible = "ti,ehci-omap"; 724 reg = <0x48064800 0x400>; 725 interrupts = <77>; 726 }; 727 }; 728 729 gpmc: gpmc@6e000000 { 730 compatible = "ti,omap3430-gpmc"; 731 ti,hwmods = "gpmc"; 732 reg = <0x6e000000 0x02d0>; 733 interrupts = <20>; 734 dmas = <&sdma 4>; 735 dma-names = "rxtx"; 736 gpmc,num-cs = <8>; 737 gpmc,num-waitpins = <4>; 738 #address-cells = <2>; 739 #size-cells = <1>; 740 interrupt-controller; 741 #interrupt-cells = <2>; 742 gpio-controller; 743 #gpio-cells = <2>; 744 }; 745 746 usb_otg_hs: usb_otg_hs@480ab000 { 747 compatible = "ti,omap3-musb"; 748 reg = <0x480ab000 0x1000>; 749 interrupts = <92>, <93>; 750 interrupt-names = "mc", "dma"; 751 ti,hwmods = "usb_otg_hs"; 752 multipoint = <1>; 753 num-eps = <16>; 754 ram-bits = <12>; 755 }; 756 757 dss: dss@48050000 { 758 compatible = "ti,omap3-dss"; 759 reg = <0x48050000 0x200>; 760 status = "disabled"; 761 ti,hwmods = "dss_core"; 762 clocks = <&dss1_alwon_fck>; 763 clock-names = "fck"; 764 #address-cells = <1>; 765 #size-cells = <1>; 766 ranges; 767 768 dispc@48050400 { 769 compatible = "ti,omap3-dispc"; 770 reg = <0x48050400 0x400>; 771 interrupts = <25>; 772 ti,hwmods = "dss_dispc"; 773 clocks = <&dss1_alwon_fck>; 774 clock-names = "fck"; 775 }; 776 777 dsi: encoder@4804fc00 { 778 compatible = "ti,omap3-dsi"; 779 reg = <0x4804fc00 0x200>, 780 <0x4804fe00 0x40>, 781 <0x4804ff00 0x20>; 782 reg-names = "proto", "phy", "pll"; 783 interrupts = <25>; 784 status = "disabled"; 785 ti,hwmods = "dss_dsi1"; 786 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; 787 clock-names = "fck", "sys_clk"; 788 }; 789 790 rfbi: encoder@48050800 { 791 compatible = "ti,omap3-rfbi"; 792 reg = <0x48050800 0x100>; 793 status = "disabled"; 794 ti,hwmods = "dss_rfbi"; 795 clocks = <&dss1_alwon_fck>, <&dss_ick>; 796 clock-names = "fck", "ick"; 797 }; 798 799 venc: encoder@48050c00 { 800 compatible = "ti,omap3-venc"; 801 reg = <0x48050c00 0x100>; 802 status = "disabled"; 803 ti,hwmods = "dss_venc"; 804 clocks = <&dss_tv_fck>; 805 clock-names = "fck"; 806 }; 807 }; 808 809 ssi: ssi-controller@48058000 { 810 compatible = "ti,omap3-ssi"; 811 ti,hwmods = "ssi"; 812 813 status = "disabled"; 814 815 reg = <0x48058000 0x1000>, 816 <0x48059000 0x1000>; 817 reg-names = "sys", 818 "gdd"; 819 820 interrupts = <71>; 821 interrupt-names = "gdd_mpu"; 822 823 #address-cells = <1>; 824 #size-cells = <1>; 825 ranges; 826 827 ssi_port1: ssi-port@4805a000 { 828 compatible = "ti,omap3-ssi-port"; 829 830 reg = <0x4805a000 0x800>, 831 <0x4805a800 0x800>; 832 reg-names = "tx", 833 "rx"; 834 835 interrupts = <67>, 836 <68>; 837 }; 838 839 ssi_port2: ssi-port@4805b000 { 840 compatible = "ti,omap3-ssi-port"; 841 842 reg = <0x4805b000 0x800>, 843 <0x4805b800 0x800>; 844 reg-names = "tx", 845 "rx"; 846 847 interrupts = <69>, 848 <70>; 849 }; 850 }; 851 }; 852 }; 853 854 /include/ "omap3xxx-clocks.dtsi" 855
