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      1 // SPDX-License-Identifier: GPL-2.0+ OR X11
      2 /*
      3  * Copyright (c) 2013 MundoReader S.L.
      4  * Author: Heiko Stuebner <heiko (a] sntech.de>
      5  */
      6 
      7 #include <dt-bindings/gpio/gpio.h>
      8 #include <dt-bindings/pinctrl/rockchip.h>
      9 #include <dt-bindings/clock/rk3188-cru.h>
     10 #include "rk3xxx.dtsi"
     11 
     12 / {
     13 	compatible = "rockchip,rk3188";
     14 
     15 	cpus {
     16 		#address-cells = <1>;
     17 		#size-cells = <0>;
     18 		enable-method = "rockchip,rk3066-smp";
     19 
     20 		cpu0: cpu@0 {
     21 			device_type = "cpu";
     22 			compatible = "arm,cortex-a9";
     23 			next-level-cache = <&L2>;
     24 			reg = <0x0>;
     25 			operating-points = <
     26 				/* kHz    uV */
     27 				1608000 1350000
     28 				1416000 1250000
     29 				1200000 1150000
     30 				1008000 1075000
     31 				 816000  975000
     32 				 600000  950000
     33 				 504000  925000
     34 				 312000  875000
     35 			>;
     36 			clock-latency = <40000>;
     37 			clocks = <&cru ARMCLK>;
     38 		};
     39 		cpu@1 {
     40 			device_type = "cpu";
     41 			compatible = "arm,cortex-a9";
     42 			next-level-cache = <&L2>;
     43 			reg = <0x1>;
     44 		};
     45 		cpu@2 {
     46 			device_type = "cpu";
     47 			compatible = "arm,cortex-a9";
     48 			next-level-cache = <&L2>;
     49 			reg = <0x2>;
     50 		};
     51 		cpu@3 {
     52 			device_type = "cpu";
     53 			compatible = "arm,cortex-a9";
     54 			next-level-cache = <&L2>;
     55 			reg = <0x3>;
     56 		};
     57 	};
     58 
     59 	sram: sram@10080000 {
     60 		compatible = "mmio-sram";
     61 		reg = <0x10080000 0x8000>;
     62 		#address-cells = <1>;
     63 		#size-cells = <1>;
     64 		ranges = <0 0x10080000 0x8000>;
     65 
     66 		smp-sram@0 {
     67 			compatible = "rockchip,rk3066-smp-sram";
     68 			reg = <0x0 0x50>;
     69 		};
     70 	};
     71 
     72 	i2s0: i2s@1011a000 {
     73 		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
     74 		reg = <0x1011a000 0x2000>;
     75 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
     76 		#address-cells = <1>;
     77 		#size-cells = <0>;
     78 		pinctrl-names = "default";
     79 		pinctrl-0 = <&i2s0_bus>;
     80 		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
     81 		dma-names = "tx", "rx";
     82 		clock-names = "i2s_hclk", "i2s_clk";
     83 		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
     84 		rockchip,playback-channels = <2>;
     85 		rockchip,capture-channels = <2>;
     86 		status = "disabled";
     87 	};
     88 
     89 	spdif: sound@1011e000 {
     90 		compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
     91 		reg = <0x1011e000 0x2000>;
     92 		#sound-dai-cells = <0>;
     93 		clock-names = "hclk", "mclk";
     94 		clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
     95 		dmas = <&dmac1_s 8>;
     96 		dma-names = "tx";
     97 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
     98 		pinctrl-names = "default";
     99 		pinctrl-0 = <&spdif_tx>;
    100 		status = "disabled";
    101 	};
    102 
    103 	cru: clock-controller@20000000 {
    104 		compatible = "rockchip,rk3188-cru";
    105 		reg = <0x20000000 0x1000>;
    106 		rockchip,grf = <&grf>;
    107 
    108 		#clock-cells = <1>;
    109 		#reset-cells = <1>;
    110 	};
    111 
    112 	efuse: efuse@20010000 {
    113 		compatible = "rockchip,rockchip-efuse";
    114 		reg = <0x20010000 0x4000>;
    115 		#address-cells = <1>;
    116 		#size-cells = <1>;
    117 		clocks = <&cru PCLK_EFUSE>;
    118 		clock-names = "pclk_efuse";
    119 
    120 		cpu_leakage: cpu_leakage@17 {
    121 			reg = <0x17 0x1>;
    122 		};
    123 	};
    124 
    125 	timer3: timer@2000e000 {
    126 		compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
    127 		reg = <0x2000e000 0x20>;
    128 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
    129 	};
    130 
    131 	usbphy: phy {
    132 		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
    133 		rockchip,grf = <&grf>;
    134 		#address-cells = <1>;
    135 		#size-cells = <0>;
    136 		status = "disabled";
    137 
    138 		usbphy0: usb-phy@10c {
    139 			#phy-cells = <0>;
    140 			reg = <0x10c>;
    141 			clocks = <&cru SCLK_OTGPHY0>;
    142 			clock-names = "phyclk";
    143 			#clock-cells = <0>;
    144 		};
    145 
    146 		usbphy1: usb-phy@11c {
    147 			#phy-cells = <0>;
    148 			reg = <0x11c>;
    149 			clocks = <&cru SCLK_OTGPHY1>;
    150 			clock-names = "phyclk";
    151 			#clock-cells = <0>;
    152 		};
    153 	};
    154 
    155 	pinctrl: pinctrl {
    156 		compatible = "rockchip,rk3188-pinctrl";
    157 		rockchip,grf = <&grf>;
    158 		rockchip,pmu = <&pmu>;
    159 
    160 		#address-cells = <1>;
    161 		#size-cells = <1>;
    162 		ranges;
    163 
    164 		gpio0: gpio0@2000a000 {
    165 			compatible = "rockchip,gpio-bank";
    166 			reg = <0x2000a000 0x100>;
    167 			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
    168 			clocks = <&cru PCLK_GPIO0>;
    169 
    170 			gpio-controller;
    171 			#gpio-cells = <2>;
    172 
    173 			interrupt-controller;
    174 			#interrupt-cells = <2>;
    175 		};
    176 
    177 		gpio1: gpio1@2003c000 {
    178 			compatible = "rockchip,gpio-bank";
    179 			reg = <0x2003c000 0x100>;
    180 			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
    181 			clocks = <&cru PCLK_GPIO1>;
    182 
    183 			gpio-controller;
    184 			#gpio-cells = <2>;
    185 
    186 			interrupt-controller;
    187 			#interrupt-cells = <2>;
    188 		};
    189 
    190 		gpio2: gpio2@2003e000 {
    191 			compatible = "rockchip,gpio-bank";
    192 			reg = <0x2003e000 0x100>;
    193 			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
    194 			clocks = <&cru PCLK_GPIO2>;
    195 
    196 			gpio-controller;
    197 			#gpio-cells = <2>;
    198 
    199 			interrupt-controller;
    200 			#interrupt-cells = <2>;
    201 		};
    202 
    203 		gpio3: gpio3@20080000 {
    204 			compatible = "rockchip,gpio-bank";
    205 			reg = <0x20080000 0x100>;
    206 			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
    207 			clocks = <&cru PCLK_GPIO3>;
    208 
    209 			gpio-controller;
    210 			#gpio-cells = <2>;
    211 
    212 			interrupt-controller;
    213 			#interrupt-cells = <2>;
    214 		};
    215 
    216 		pcfg_pull_up: pcfg_pull_up {
    217 			bias-pull-up;
    218 		};
    219 
    220 		pcfg_pull_down: pcfg_pull_down {
    221 			bias-pull-down;
    222 		};
    223 
    224 		pcfg_pull_none: pcfg_pull_none {
    225 			bias-disable;
    226 		};
    227 
    228 		emmc {
    229 			emmc_clk: emmc-clk {
    230 				rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
    231 			};
    232 
    233 			emmc_cmd: emmc-cmd {
    234 				rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
    235 			};
    236 
    237 			emmc_rst: emmc-rst {
    238 				rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
    239 			};
    240 
    241 			/*
    242 			 * The data pins are shared between nandc and emmc and
    243 			 * not accessible through pinctrl. Also they should've
    244 			 * been already set correctly by firmware, as
    245 			 * flash/emmc is the boot-device.
    246 			 */
    247 		};
    248 
    249 		emac {
    250 			emac_xfer: emac-xfer {
    251 				rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
    252 						<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
    253 						<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
    254 						<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
    255 						<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
    256 						<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
    257 						<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
    258 						<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
    259 			};
    260 
    261 			emac_mdio: emac-mdio {
    262 				rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
    263 						<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
    264 			};
    265 		};
    266 
    267 		i2c0 {
    268 			i2c0_xfer: i2c0-xfer {
    269 				rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
    270 						<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
    271 			};
    272 		};
    273 
    274 		i2c1 {
    275 			i2c1_xfer: i2c1-xfer {
    276 				rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
    277 						<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
    278 			};
    279 		};
    280 
    281 		i2c2 {
    282 			i2c2_xfer: i2c2-xfer {
    283 				rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
    284 						<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
    285 			};
    286 		};
    287 
    288 		i2c3 {
    289 			i2c3_xfer: i2c3-xfer {
    290 				rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
    291 						<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
    292 			};
    293 		};
    294 
    295 		i2c4 {
    296 			i2c4_xfer: i2c4-xfer {
    297 				rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
    298 						<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
    299 			};
    300 		};
    301 
    302 		pwm0 {
    303 			pwm0_out: pwm0-out {
    304 				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
    305 			};
    306 		};
    307 
    308 		pwm1 {
    309 			pwm1_out: pwm1-out {
    310 				rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
    311 			};
    312 		};
    313 
    314 		pwm2 {
    315 			pwm2_out: pwm2-out {
    316 				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
    317 			};
    318 		};
    319 
    320 		pwm3 {
    321 			pwm3_out: pwm3-out {
    322 				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
    323 			};
    324 		};
    325 
    326 		spi0 {
    327 			spi0_clk: spi0-clk {
    328 				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
    329 			};
    330 			spi0_cs0: spi0-cs0 {
    331 				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
    332 			};
    333 			spi0_tx: spi0-tx {
    334 				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
    335 			};
    336 			spi0_rx: spi0-rx {
    337 				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
    338 			};
    339 			spi0_cs1: spi0-cs1 {
    340 				rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
    341 			};
    342 		};
    343 
    344 		spi1 {
    345 			spi1_clk: spi1-clk {
    346 				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
    347 			};
    348 			spi1_cs0: spi1-cs0 {
    349 				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
    350 			};
    351 			spi1_rx: spi1-rx {
    352 				rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
    353 			};
    354 			spi1_tx: spi1-tx {
    355 				rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
    356 			};
    357 			spi1_cs1: spi1-cs1 {
    358 				rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
    359 			};
    360 		};
    361 
    362 		uart0 {
    363 			uart0_xfer: uart0-xfer {
    364 				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
    365 						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
    366 			};
    367 
    368 			uart0_cts: uart0-cts {
    369 				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
    370 			};
    371 
    372 			uart0_rts: uart0-rts {
    373 				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
    374 			};
    375 		};
    376 
    377 		uart1 {
    378 			uart1_xfer: uart1-xfer {
    379 				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
    380 						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
    381 			};
    382 
    383 			uart1_cts: uart1-cts {
    384 				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
    385 			};
    386 
    387 			uart1_rts: uart1-rts {
    388 				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
    389 			};
    390 		};
    391 
    392 		uart2 {
    393 			uart2_xfer: uart2-xfer {
    394 				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
    395 						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
    396 			};
    397 			/* no rts / cts for uart2 */
    398 		};
    399 
    400 		uart3 {
    401 			uart3_xfer: uart3-xfer {
    402 				rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
    403 						<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
    404 			};
    405 
    406 			uart3_cts: uart3-cts {
    407 				rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
    408 			};
    409 
    410 			uart3_rts: uart3-rts {
    411 				rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
    412 			};
    413 		};
    414 
    415 		sd0 {
    416 			sd0_clk: sd0-clk {
    417 				rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
    418 			};
    419 
    420 			sd0_cmd: sd0-cmd {
    421 				rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
    422 			};
    423 
    424 			sd0_cd: sd0-cd {
    425 				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
    426 			};
    427 
    428 			sd0_wp: sd0-wp {
    429 				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
    430 			};
    431 
    432 			sd0_pwr: sd0-pwr {
    433 				rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
    434 			};
    435 
    436 			sd0_bus1: sd0-bus-width1 {
    437 				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
    438 			};
    439 
    440 			sd0_bus4: sd0-bus-width4 {
    441 				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
    442 						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
    443 						<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
    444 						<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
    445 			};
    446 		};
    447 
    448 		sd1 {
    449 			sd1_clk: sd1-clk {
    450 				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
    451 			};
    452 
    453 			sd1_cmd: sd1-cmd {
    454 				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
    455 			};
    456 
    457 			sd1_cd: sd1-cd {
    458 				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
    459 			};
    460 
    461 			sd1_wp: sd1-wp {
    462 				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
    463 			};
    464 
    465 			sd1_bus1: sd1-bus-width1 {
    466 				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
    467 			};
    468 
    469 			sd1_bus4: sd1-bus-width4 {
    470 				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
    471 						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
    472 						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
    473 						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
    474 			};
    475 		};
    476 
    477 		i2s0 {
    478 			i2s0_bus: i2s0-bus {
    479 				rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
    480 						<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
    481 						<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
    482 						<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
    483 						<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
    484 						<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
    485 			};
    486 		};
    487 
    488 		spdif {
    489 			spdif_tx: spdif-tx {
    490 				rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
    491 			};
    492 		};
    493 	};
    494 };
    495 
    496 &emac {
    497 	compatible = "rockchip,rk3188-emac";
    498 };
    499 
    500 &global_timer {
    501 	interrupts = <GIC_PPI 11 0xf04>;
    502 };
    503 
    504 &grf {
    505 	compatible = "rockchip,rk3188-grf", "syscon";
    506 };
    507 
    508 &local_timer {
    509 	interrupts = <GIC_PPI 13 0xf04>;
    510 };
    511 
    512 &i2c0 {
    513 	compatible = "rockchip,rk3188-i2c";
    514 	pinctrl-names = "default";
    515 	pinctrl-0 = <&i2c0_xfer>;
    516 };
    517 
    518 &i2c1 {
    519 	compatible = "rockchip,rk3188-i2c";
    520 	pinctrl-names = "default";
    521 	pinctrl-0 = <&i2c1_xfer>;
    522 };
    523 
    524 &i2c2 {
    525 	compatible = "rockchip,rk3188-i2c";
    526 	pinctrl-names = "default";
    527 	pinctrl-0 = <&i2c2_xfer>;
    528 };
    529 
    530 &i2c3 {
    531 	compatible = "rockchip,rk3188-i2c";
    532 	pinctrl-names = "default";
    533 	pinctrl-0 = <&i2c3_xfer>;
    534 };
    535 
    536 &i2c4 {
    537 	compatible = "rockchip,rk3188-i2c";
    538 	pinctrl-names = "default";
    539 	pinctrl-0 = <&i2c4_xfer>;
    540 };
    541 
    542 &pmu {
    543 	compatible = "rockchip,rk3188-pmu", "syscon";
    544 };
    545 
    546 &pwm0 {
    547 	pinctrl-names = "default";
    548 	pinctrl-0 = <&pwm0_out>;
    549 };
    550 
    551 &pwm1 {
    552 	pinctrl-names = "default";
    553 	pinctrl-0 = <&pwm1_out>;
    554 };
    555 
    556 &pwm2 {
    557 	pinctrl-names = "default";
    558 	pinctrl-0 = <&pwm2_out>;
    559 };
    560 
    561 &pwm3 {
    562 	pinctrl-names = "default";
    563 	pinctrl-0 = <&pwm3_out>;
    564 };
    565 
    566 &spi0 {
    567 	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
    568 	pinctrl-names = "default";
    569 	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
    570 };
    571 
    572 &spi1 {
    573 	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
    574 	pinctrl-names = "default";
    575 	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
    576 };
    577 
    578 &uart0 {
    579 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
    580 	pinctrl-names = "default";
    581 	pinctrl-0 = <&uart0_xfer>;
    582 };
    583 
    584 &uart1 {
    585 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
    586 	pinctrl-names = "default";
    587 	pinctrl-0 = <&uart1_xfer>;
    588 };
    589 
    590 &uart2 {
    591 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
    592 	pinctrl-names = "default";
    593 	pinctrl-0 = <&uart2_xfer>;
    594 };
    595 
    596 &uart3 {
    597 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
    598 	pinctrl-names = "default";
    599 	pinctrl-0 = <&uart3_xfer>;
    600 };
    601 
    602 &wdt {
    603 	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
    604 };
    605