1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/clock/rk3228-cru.h> 11 #include <dt-bindings/thermal/thermal.h> 12 13 / { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 interrupt-parent = <&gic>; 18 19 aliases { 20 serial0 = &uart0; 21 serial1 = &uart1; 22 serial2 = &uart2; 23 mmc0 = &emmc; 24 mmc1 = &sdmmc; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@f00 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a7"; 34 reg = <0xf00>; 35 resets = <&cru SRST_CORE0>; 36 operating-points = < 37 /* KHz uV */ 38 816000 1000000 39 >; 40 #cooling-cells = <2>; /* min followed by max */ 41 clock-latency = <40000>; 42 clocks = <&cru ARMCLK>; 43 }; 44 45 cpu1: cpu@f01 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a7"; 48 reg = <0xf01>; 49 resets = <&cru SRST_CORE1>; 50 }; 51 52 cpu2: cpu@f02 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a7"; 55 reg = <0xf02>; 56 resets = <&cru SRST_CORE2>; 57 }; 58 59 cpu3: cpu@f03 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf03>; 63 resets = <&cru SRST_CORE3>; 64 }; 65 }; 66 67 amba { 68 compatible = "simple-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges; 72 73 pdma: pdma@110f0000 { 74 compatible = "arm,pl330", "arm,primecell"; 75 reg = <0x110f0000 0x4000>; 76 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 78 #dma-cells = <1>; 79 clocks = <&cru ACLK_DMAC>; 80 clock-names = "apb_pclk"; 81 }; 82 }; 83 84 arm-pmu { 85 compatible = "arm,cortex-a7-pmu"; 86 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 90 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 91 }; 92 93 timer { 94 compatible = "arm,armv7-timer"; 95 arm,cpu-registers-not-fw-configured; 96 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 100 clock-frequency = <24000000>; 101 }; 102 103 xin24m: oscillator { 104 compatible = "fixed-clock"; 105 clock-frequency = <24000000>; 106 clock-output-names = "xin24m"; 107 #clock-cells = <0>; 108 }; 109 110 bus_intmem@10080000 { 111 compatible = "mmio-sram"; 112 reg = <0x10080000 0x9000>; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 ranges = <0 0x10080000 0x9000>; 116 smp-sram@0 { 117 compatible = "rockchip,rk322x-smp-sram"; 118 reg = <0x00 0x10>; 119 }; 120 ddr_sram: ddr-sram@1000 { 121 compatible = "rockchip,rk322x-ddr-sram"; 122 reg = <0x1000 0x8000>; 123 }; 124 }; 125 126 i2s1: i2s1@100b0000 { 127 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 128 reg = <0x100b0000 0x4000>; 129 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 clock-names = "i2s_clk", "i2s_hclk"; 133 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 134 dmas = <&pdma 14>, <&pdma 15>; 135 dma-names = "tx", "rx"; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&i2s1_bus>; 138 status = "disabled"; 139 }; 140 141 i2s0: i2s0@100c0000 { 142 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 143 reg = <0x100c0000 0x4000>; 144 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 145 #address-cells = <1>; 146 #size-cells = <0>; 147 clock-names = "i2s_clk", "i2s_hclk"; 148 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 149 dmas = <&pdma 11>, <&pdma 12>; 150 dma-names = "tx", "rx"; 151 status = "disabled"; 152 }; 153 154 i2s2: i2s2@100e0000 { 155 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 156 reg = <0x100e0000 0x4000>; 157 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 clock-names = "i2s_clk", "i2s_hclk"; 161 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 162 dmas = <&pdma 0>, <&pdma 1>; 163 dma-names = "tx", "rx"; 164 status = "disabled"; 165 }; 166 167 grf: syscon@11000000 { 168 u-boot,dm-pre-reloc; 169 compatible = "rockchip,rk3228-grf", "syscon"; 170 reg = <0x11000000 0x1000>; 171 }; 172 173 uart0: serial@11010000 { 174 compatible = "snps,dw-apb-uart"; 175 reg = <0x11010000 0x100>; 176 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 177 clock-frequency = <24000000>; 178 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 179 clock-names = "baudclk", "apb_pclk"; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 182 reg-shift = <2>; 183 reg-io-width = <4>; 184 status = "disabled"; 185 }; 186 187 uart1: serial@11020000 { 188 compatible = "snps,dw-apb-uart"; 189 reg = <0x11020000 0x100>; 190 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 191 clock-frequency = <24000000>; 192 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 193 clock-names = "baudclk", "apb_pclk"; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&uart1_xfer>; 196 reg-shift = <2>; 197 reg-io-width = <4>; 198 status = "disabled"; 199 }; 200 201 uart2: serial@11030000 { 202 compatible = "snps,dw-apb-uart"; 203 reg = <0x11030000 0x100>; 204 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 205 clock-frequency = <24000000>; 206 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 207 clock-names = "baudclk", "apb_pclk"; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&uart2_xfer>; 210 reg-shift = <2>; 211 reg-io-width = <4>; 212 status = "disabled"; 213 }; 214 215 i2c0: i2c@11050000 { 216 compatible = "rockchip,rk3228-i2c"; 217 reg = <0x11050000 0x1000>; 218 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 clock-names = "i2c"; 222 clocks = <&cru PCLK_I2C0>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&i2c0_xfer>; 225 status = "disabled"; 226 }; 227 228 i2c1: i2c@11060000 { 229 compatible = "rockchip,rk3228-i2c"; 230 reg = <0x11060000 0x1000>; 231 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 clock-names = "i2c"; 235 clocks = <&cru PCLK_I2C1>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&i2c1_xfer>; 238 status = "disabled"; 239 }; 240 241 i2c2: i2c@11070000 { 242 compatible = "rockchip,rk3228-i2c"; 243 reg = <0x11070000 0x1000>; 244 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 clock-names = "i2c"; 248 clocks = <&cru PCLK_I2C2>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&i2c2_xfer>; 251 status = "disabled"; 252 }; 253 254 i2c3: i2c@11080000 { 255 compatible = "rockchip,rk3228-i2c"; 256 reg = <0x11080000 0x1000>; 257 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 clock-names = "i2c"; 261 clocks = <&cru PCLK_I2C3>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&i2c3_xfer>; 264 status = "disabled"; 265 }; 266 267 pwm0: pwm@110b0000 { 268 compatible = "rockchip,rk3288-pwm"; 269 reg = <0x110b0000 0x10>; 270 #pwm-cells = <3>; 271 clocks = <&cru PCLK_PWM>; 272 clock-names = "pwm"; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pwm0_pin>; 275 status = "disabled"; 276 }; 277 278 pwm1: pwm@110b0010 { 279 compatible = "rockchip,rk3288-pwm"; 280 reg = <0x110b0010 0x10>; 281 #pwm-cells = <3>; 282 clocks = <&cru PCLK_PWM>; 283 clock-names = "pwm"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pwm1_pin>; 286 status = "disabled"; 287 }; 288 289 pwm2: pwm@110b0020 { 290 compatible = "rockchip,rk3288-pwm"; 291 reg = <0x110b0020 0x10>; 292 #pwm-cells = <3>; 293 clocks = <&cru PCLK_PWM>; 294 clock-names = "pwm"; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pwm2_pin>; 297 status = "disabled"; 298 }; 299 300 pwm3: pwm@110b0030 { 301 compatible = "rockchip,rk3288-pwm"; 302 reg = <0x110b0030 0x10>; 303 #pwm-cells = <2>; 304 clocks = <&cru PCLK_PWM>; 305 clock-names = "pwm"; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pwm3_pin>; 308 status = "disabled"; 309 }; 310 311 timer: timer@110c0000 { 312 compatible = "rockchip,rk3288-timer"; 313 reg = <0x110c0000 0x20>; 314 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&xin24m>, <&cru PCLK_TIMER>; 316 clock-names = "timer", "pclk"; 317 }; 318 319 cru: clock-controller@110e0000 { 320 u-boot,dm-pre-reloc; 321 compatible = "rockchip,rk3228-cru"; 322 reg = <0x110e0000 0x1000>; 323 rockchip,grf = <&grf>; 324 #clock-cells = <1>; 325 #reset-cells = <1>; 326 assigned-clocks = <&cru PLL_GPLL>; 327 assigned-clock-rates = <594000000>; 328 }; 329 330 thermal-zones { 331 cpu_thermal: cpu-thermal { 332 polling-delay-passive = <100>; /* milliseconds */ 333 polling-delay = <5000>; /* milliseconds */ 334 335 thermal-sensors = <&tsadc 0>; 336 337 trips { 338 cpu_alert0: cpu_alert0 { 339 temperature = <70000>; /* millicelsius */ 340 hysteresis = <2000>; /* millicelsius */ 341 type = "passive"; 342 }; 343 cpu_alert1: cpu_alert1 { 344 temperature = <75000>; /* millicelsius */ 345 hysteresis = <2000>; /* millicelsius */ 346 type = "passive"; 347 }; 348 cpu_crit: cpu_crit { 349 temperature = <90000>; /* millicelsius */ 350 hysteresis = <2000>; /* millicelsius */ 351 type = "critical"; 352 }; 353 }; 354 355 cooling-maps { 356 map0 { 357 trip = <&cpu_alert0>; 358 cooling-device = 359 <&cpu0 THERMAL_NO_LIMIT 6>; 360 }; 361 map1 { 362 trip = <&cpu_alert1>; 363 cooling-device = 364 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 365 }; 366 }; 367 }; 368 }; 369 370 tsadc: tsadc@11150000 { 371 compatible = "rockchip,rk3228-tsadc"; 372 reg = <0x11150000 0x100>; 373 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 375 clock-names = "tsadc", "apb_pclk"; 376 resets = <&cru SRST_TSADC>; 377 reset-names = "tsadc-apb"; 378 pinctrl-names = "init", "default", "sleep"; 379 pinctrl-0 = <&otp_gpio>; 380 pinctrl-1 = <&otp_out>; 381 pinctrl-2 = <&otp_gpio>; 382 #thermal-sensor-cells = <0>; 383 rockchip,hw-tshut-temp = <95000>; 384 status = "disabled"; 385 }; 386 387 sdmmc: dwmmc@30000000 { 388 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 389 reg = <0x30000000 0x4000>; 390 max-frequency = <150000000>; 391 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 393 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 394 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 395 fifo-depth = <0x100>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 398 status = "disabled"; 399 }; 400 401 sdio: dwmmc@30010000 { 402 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 403 reg = <0x30010000 0x4000>; 404 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 406 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 407 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 408 fifo-depth = <0x100>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 411 status = "disabled"; 412 }; 413 414 emmc: dwmmc@30020000 { 415 compatible = "rockchip,rk3288-dw-mshc"; 416 reg = <0x30020000 0x4000>; 417 max-frequency = <150000000>; 418 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 420 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 421 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 422 bus-width = <8>; 423 default-sample-phase = <158>; 424 num-slots = <1>; 425 fifo-depth = <0x100>; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 428 resets = <&cru SRST_EMMC>; 429 reset-names = "reset"; 430 status = "disabled"; 431 }; 432 433 usb20_otg: usb@30040000 { 434 compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", 435 "snps,dwc2"; 436 reg = <0x30040000 0x40000>; 437 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 438 hnp-srp-disable; 439 dr_mode = "otg"; 440 status = "disabled"; 441 }; 442 443 gmac: ethernet@30200000 { 444 compatible = "rockchip,rk3228-gmac"; 445 reg = <0x30200000 0x10000>; 446 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 447 interrupt-names = "macirq"; 448 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 449 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 450 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 451 <&cru PCLK_GMAC>; 452 clock-names = "stmmaceth", "mac_clk_rx", 453 "mac_clk_tx", "clk_mac_ref", 454 "clk_mac_refout", "aclk_mac", 455 "pclk_mac"; 456 resets = <&cru SRST_GMAC>; 457 reset-names = "stmmaceth"; 458 rockchip,grf = <&grf>; 459 status = "disabled"; 460 }; 461 462 gic: interrupt-controller@32010000 { 463 compatible = "arm,gic-400"; 464 interrupt-controller; 465 #interrupt-cells = <3>; 466 #address-cells = <0>; 467 468 reg = <0x32011000 0x1000>, 469 <0x32012000 0x2000>, 470 <0x32014000 0x2000>, 471 <0x32016000 0x2000>; 472 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 473 }; 474 475 pinctrl: pinctrl { 476 compatible = "rockchip,rk3228-pinctrl"; 477 rockchip,grf = <&grf>; 478 #address-cells = <1>; 479 #size-cells = <1>; 480 ranges; 481 482 gpio0: gpio0@11110000 { 483 compatible = "rockchip,gpio-bank"; 484 reg = <0x11110000 0x100>; 485 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&cru PCLK_GPIO0>; 487 488 gpio-controller; 489 #gpio-cells = <2>; 490 491 interrupt-controller; 492 #interrupt-cells = <2>; 493 }; 494 495 gpio1: gpio1@11120000 { 496 compatible = "rockchip,gpio-bank"; 497 reg = <0x11120000 0x100>; 498 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&cru PCLK_GPIO1>; 500 501 gpio-controller; 502 #gpio-cells = <2>; 503 504 interrupt-controller; 505 #interrupt-cells = <2>; 506 }; 507 508 gpio2: gpio2@11130000 { 509 compatible = "rockchip,gpio-bank"; 510 reg = <0x11130000 0x100>; 511 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&cru PCLK_GPIO2>; 513 514 gpio-controller; 515 #gpio-cells = <2>; 516 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 }; 520 521 gpio3: gpio3@11140000 { 522 compatible = "rockchip,gpio-bank"; 523 reg = <0x11140000 0x100>; 524 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&cru PCLK_GPIO3>; 526 527 gpio-controller; 528 #gpio-cells = <2>; 529 530 interrupt-controller; 531 #interrupt-cells = <2>; 532 }; 533 534 pcfg_pull_up: pcfg-pull-up { 535 bias-pull-up; 536 }; 537 538 pcfg_pull_down: pcfg-pull-down { 539 bias-pull-down; 540 }; 541 542 pcfg_pull_none: pcfg-pull-none { 543 bias-disable; 544 }; 545 546 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 547 drive-strength = <12>; 548 }; 549 550 sdmmc { 551 sdmmc_clk: sdmmc-clk { 552 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 553 }; 554 555 sdmmc_cmd: sdmmc-cmd { 556 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 557 }; 558 559 sdmmc_bus4: sdmmc-bus4 { 560 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 561 <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 562 <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 563 <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 564 }; 565 }; 566 567 sdio { 568 sdio_clk: sdio-clk { 569 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 570 }; 571 572 sdio_cmd: sdio-cmd { 573 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 574 }; 575 576 sdio_bus4: sdio-bus4 { 577 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 578 <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 579 <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 580 <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 581 }; 582 }; 583 584 emmc { 585 emmc_clk: emmc-clk { 586 rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 587 }; 588 589 emmc_cmd: emmc-cmd { 590 rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 591 }; 592 593 emmc_bus8: emmc-bus8 { 594 rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, 595 <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, 596 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, 597 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, 598 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, 599 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 600 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, 601 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 602 }; 603 }; 604 605 gmac { 606 rgmii_pins: rgmii-pins { 607 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 608 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 609 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 610 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 611 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 612 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 613 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 614 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 615 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 616 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 617 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 618 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 619 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 620 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 621 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 622 }; 623 624 rmii_pins: rmii-pins { 625 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 626 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 627 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 628 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 629 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 630 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 631 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 632 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 633 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 634 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 635 }; 636 637 phy_pins: phy-pins { 638 rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, 639 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 640 }; 641 }; 642 643 i2c0 { 644 i2c0_xfer: i2c0-xfer { 645 rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 646 <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 647 }; 648 }; 649 650 i2c1 { 651 i2c1_xfer: i2c1-xfer { 652 rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 653 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 654 }; 655 }; 656 657 i2c2 { 658 i2c2_xfer: i2c2-xfer { 659 rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 660 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 661 }; 662 }; 663 664 i2c3 { 665 i2c3_xfer: i2c3-xfer { 666 rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 667 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 668 }; 669 }; 670 671 i2s1 { 672 i2s1_bus: i2s1-bus { 673 rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 674 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 675 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 676 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 677 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 678 <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 679 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 680 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 681 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 682 }; 683 }; 684 685 pwm0 { 686 pwm0_pin: pwm0-pin { 687 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 688 }; 689 }; 690 691 pwm1 { 692 pwm1_pin: pwm1-pin { 693 rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 694 }; 695 }; 696 697 pwm2 { 698 pwm2_pin: pwm2-pin { 699 rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 700 }; 701 }; 702 703 pwm3 { 704 pwm3_pin: pwm3-pin { 705 rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 706 }; 707 }; 708 709 tsadc { 710 otp_gpio: otp-gpio { 711 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 712 }; 713 714 otp_out: otp-out { 715 rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 716 }; 717 }; 718 719 uart0 { 720 uart0_xfer: uart0-xfer { 721 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 722 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; 723 }; 724 725 uart0_cts: uart0-cts { 726 rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 727 }; 728 729 uart0_rts: uart0-rts { 730 rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 731 }; 732 }; 733 734 uart1 { 735 uart1_xfer: uart1-xfer { 736 rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 737 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 738 }; 739 740 uart1_cts: uart1-cts { 741 rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 742 }; 743 744 uart1_rts: uart1-rts { 745 rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 746 }; 747 }; 748 749 uart2 { 750 uart2_xfer: uart2-xfer { 751 rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, 752 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 753 }; 754 755 uart2_cts: uart2-cts { 756 rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 757 }; 758 759 uart2_rts: uart2-rts { 760 rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 761 }; 762 }; 763 }; 764 765 dmc: dmc@11200000 { 766 u-boot,dm-pre-reloc; 767 compatible = "rockchip,rk3228-dmc", "syscon"; 768 rockchip,cru = <&cru>; 769 rockchip,grf = <&grf>; 770 rockchip,msch = <&service_msch>; 771 reg = <0x11200000 0x3fc 772 0x12000000 0x400>; 773 rockchip,sram = <&ddr_sram>; 774 }; 775 776 service_msch: syscon@31090000 { 777 u-boot,dm-pre-reloc; 778 compatible = "rockchip,rk3228-msch", "syscon"; 779 reg = <0x31090000 0x2000>; 780 }; 781 }; 782
