1 /* 2 * Device tree file for Phytec phyCORE-RK3288 SoM 3 * Copyright (C) 2017 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <w.egorov (at) phytec.de> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45 #include <dt-bindings/net/ti-dp83867.h> 46 #include "rk3288.dtsi" 47 48 / { 49 model = "Phytec RK3288 phyCORE"; 50 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; 51 52 /* 53 * Set the minimum memory size here and 54 * let the bootloader set the real size. 55 */ 56 memory { 57 device_type = "memory"; 58 reg = <0 0x8000000>; 59 }; 60 61 aliases { 62 rtc0 = &i2c_rtc; 63 rtc1 = &rk818; 64 eeprom0 = &i2c_eeprom_id; 65 }; 66 67 ext_gmac: external-gmac-clock { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <125000000>; 71 clock-output-names = "ext_gmac"; 72 }; 73 74 io_domains: io_domains { 75 compatible = "rockchip,rk3288-io-voltage-domain"; 76 77 status = "okay"; 78 sdcard-supply = <&vdd_io_sd>; 79 flash0-supply = <&vdd_emmc_io>; 80 flash1-supply = <&vdd_misc_1v8>; 81 gpio1830-supply = <&vdd_3v3_io>; 82 gpio30-supply = <&vdd_3v3_io>; 83 bb-supply = <&vdd_3v3_io>; 84 dvp-supply = <&vdd_3v3_io>; 85 lcdc-supply = <&vdd_3v3_io>; 86 wifi-supply = <&vdd_3v3_io>; 87 audio-supply = <&vdd_3v3_io>; 88 }; 89 90 leds: user-leds { 91 compatible = "gpio-leds"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&user_led>; 94 95 user { 96 label = "green_led"; 97 gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 98 linux,default-trigger = "heartbeat"; 99 default-state = "keep"; 100 }; 101 }; 102 103 vdd_emmc_io: vdd-emmc-io { 104 compatible = "regulator-fixed"; 105 regulator-name = "vdd_emmc_io"; 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 vin-supply = <&vdd_3v3_io>; 109 }; 110 111 vdd_in_otg_out: vdd-in-otg-out { 112 compatible = "regulator-fixed"; 113 regulator-name = "vdd_in_otg_out"; 114 regulator-always-on; 115 regulator-boot-on; 116 regulator-min-microvolt = <5000000>; 117 regulator-max-microvolt = <5000000>; 118 }; 119 120 vdd_misc_1v8: vdd-misc-1v8 { 121 compatible = "regulator-fixed"; 122 regulator-name = "vdd_misc_1v8"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <1800000>; 126 regulator-max-microvolt = <1800000>; 127 }; 128 }; 129 130 &cpu0 { 131 cpu0-supply = <&vdd_cpu>; 132 operating-points = < 133 /* KHz uV */ 134 1800000 1400000 135 1608000 1350000 136 1512000 1300000 137 1416000 1200000 138 1200000 1100000 139 1008000 1050000 140 816000 1000000 141 696000 950000 142 600000 900000 143 408000 900000 144 312000 900000 145 216000 900000 146 126000 900000 147 >; 148 }; 149 150 &emmc { 151 status = "okay"; 152 u-boot,dm-pre-reloc; 153 154 bus-width = <8>; 155 cap-mmc-highspeed; 156 disable-wp; 157 non-removable; 158 num-slots = <1>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; 161 vmmc-supply = <&vdd_3v3_io>; 162 vqmmc-supply = <&vdd_emmc_io>; 163 }; 164 165 &gmac { 166 assigned-clocks = <&cru SCLK_MAC>; 167 assigned-clock-parents = <&ext_gmac>; 168 clock_in_out = "input"; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; 171 phy-handle = <&phy0>; 172 phy-supply = <&vdd_eth_2v5>; 173 phy-mode = "rgmii-id"; 174 snps,reset-active-low; 175 snps,reset-delays-us = <0 10000 1000000>; 176 snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; 177 tx_delay = <0x0>; 178 rx_delay = <0x0>; 179 180 mdio0 { 181 compatible = "snps,dwmac-mdio"; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 185 phy0: ethernet-phy@0 { 186 compatible = "ethernet-phy-ieee802.3-c22"; 187 reg = <0>; 188 interrupt-parent = <&gpio4>; 189 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 190 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 191 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 192 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 193 enet-phy-lane-no-swap; 194 }; 195 }; 196 }; 197 198 &hdmi { 199 ddc-i2c-bus = <&i2c5>; 200 }; 201 202 &i2c0 { 203 status = "okay"; 204 u-boot,dm-pre-reloc; 205 206 clock-frequency = <400000>; 207 208 rk818: pmic@1c { 209 status = "okay"; 210 compatible = "rockchip,rk818"; 211 reg = <0x1c>; 212 interrupt-parent = <&gpio0>; 213 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pmic_int>; 216 rockchip,system-power-controller; 217 wakeup-source; 218 #clock-cells = <1>; 219 u-boot,dm-pre-reloc; 220 221 vcc1-supply = <&vdd_sys>; 222 vcc2-supply = <&vdd_sys>; 223 vcc3-supply = <&vdd_sys>; 224 vcc4-supply = <&vdd_sys>; 225 boost-supply = <&vdd_in_otg_out>; 226 vcc6-supply = <&vdd_sys>; 227 vcc7-supply = <&vdd_misc_1v8>; 228 vcc8-supply = <&vdd_misc_1v8>; 229 vcc9-supply = <&vdd_3v3_io>; 230 vddio-supply = <&vdd_3v3_io>; 231 232 regulators { 233 u-boot,dm-pre-reloc; 234 vdd_log: DCDC_REG1 { 235 regulator-name = "vdd_log"; 236 regulator-always-on; 237 regulator-boot-on; 238 regulator-min-microvolt = <1100000>; 239 regulator-max-microvolt = <1100000>; 240 regulator-state-mem { 241 regulator-off-in-suspend; 242 }; 243 }; 244 245 vdd_gpu: DCDC_REG2 { 246 regulator-name = "vdd_gpu"; 247 regulator-always-on; 248 regulator-boot-on; 249 regulator-min-microvolt = <800000>; 250 regulator-max-microvolt = <1250000>; 251 regulator-state-mem { 252 regulator-on-in-suspend; 253 regulator-suspend-microvolt = <1000000>; 254 }; 255 }; 256 257 vcc_ddr: DCDC_REG3 { 258 regulator-name = "vcc_ddr"; 259 regulator-always-on; 260 regulator-boot-on; 261 regulator-state-mem { 262 regulator-on-in-suspend; 263 }; 264 }; 265 266 vdd_3v3_io: DCDC_REG4 { 267 regulator-name = "vdd_3v3_io"; 268 regulator-always-on; 269 regulator-boot-on; 270 regulator-min-microvolt = <3300000>; 271 regulator-max-microvolt = <3300000>; 272 regulator-state-mem { 273 regulator-on-in-suspend; 274 regulator-suspend-microvolt = <3300000>; 275 }; 276 }; 277 278 vdd_sys: DCDC_BOOST { 279 regulator-name = "vdd_sys"; 280 regulator-always-on; 281 regulator-boot-on; 282 regulator-min-microvolt = <5000000>; 283 regulator-max-microvolt = <5000000>; 284 regulator-state-mem { 285 regulator-on-in-suspend; 286 regulator-suspend-microvolt = <5000000>; 287 }; 288 }; 289 290 /* vcc9 */ 291 vdd_sd: SWITCH_REG { 292 regulator-name = "vdd_sd"; 293 regulator-always-on; 294 regulator-boot-on; 295 regulator-state-mem { 296 regulator-off-in-suspend; 297 }; 298 }; 299 300 /* vcc6 */ 301 vdd_eth_2v5: LDO_REG2 { 302 regulator-name = "vdd_eth_2v5"; 303 regulator-always-on; 304 regulator-boot-on; 305 regulator-min-microvolt = <2500000>; 306 regulator-max-microvolt = <2500000>; 307 regulator-state-mem { 308 regulator-on-in-suspend; 309 regulator-suspend-microvolt = <2500000>; 310 }; 311 }; 312 313 /* vcc7 */ 314 vdd_1v0: LDO_REG3 { 315 regulator-name = "vdd_1v0"; 316 regulator-always-on; 317 regulator-boot-on; 318 regulator-min-microvolt = <1000000>; 319 regulator-max-microvolt = <1000000>; 320 regulator-state-mem { 321 regulator-on-in-suspend; 322 regulator-suspend-microvolt = <1000000>; 323 }; 324 }; 325 326 /* vcc8 */ 327 vdd_1v8_lcd_ldo: LDO_REG4 { 328 regulator-name = "vdd_1v8_lcd_ldo"; 329 regulator-always-on; 330 regulator-boot-on; 331 regulator-min-microvolt = <1800000>; 332 regulator-max-microvolt = <1800000>; 333 regulator-state-mem { 334 regulator-on-in-suspend; 335 regulator-suspend-microvolt = <1800000>; 336 }; 337 }; 338 339 /* vcc8 */ 340 vdd_1v0_lcd: LDO_REG6 { 341 regulator-name = "vdd_1v0_lcd"; 342 regulator-always-on; 343 regulator-boot-on; 344 regulator-min-microvolt = <1000000>; 345 regulator-max-microvolt = <1000000>; 346 regulator-state-mem { 347 regulator-on-in-suspend; 348 regulator-suspend-microvolt = <1000000>; 349 }; 350 }; 351 352 /* vcc7 */ 353 vdd_1v8_ldo: LDO_REG7 { 354 regulator-name = "vdd_1v8_ldo"; 355 regulator-always-on; 356 regulator-boot-on; 357 regulator-min-microvolt = <1800000>; 358 regulator-max-microvolt = <1800000>; 359 regulator-state-mem { 360 regulator-off-in-suspend; 361 regulator-suspend-microvolt = <1800000>; 362 }; 363 }; 364 365 /* vcc9 */ 366 vdd_io_sd: LDO_REG9 { 367 regulator-name = "vdd_io_sd"; 368 regulator-always-on; 369 regulator-boot-on; 370 regulator-min-microvolt = <3300000>; 371 regulator-max-microvolt = <3300000>; 372 regulator-state-mem { 373 regulator-on-in-suspend; 374 regulator-suspend-microvolt = <3300000>; 375 }; 376 }; 377 }; 378 }; 379 380 /* M24C32-D */ 381 i2c_eeprom: eeprom@50 { 382 compatible = "atmel,24c32"; 383 reg = <0x50>; 384 pagesize = <32>; 385 }; 386 387 /* M24C32-D Identification page */ 388 i2c_eeprom_id: eeprom@58 { 389 compatible = "atmel,24c32"; 390 reg = <0x58>; 391 pagesize = <32>; 392 }; 393 394 vdd_cpu: regulator@60 { 395 compatible = "fcs,fan53555"; 396 reg = <0x60>; 397 fcs,suspend-voltage-selector = <1>; 398 regulator-always-on; 399 regulator-boot-on; 400 regulator-enable-ramp-delay = <300>; 401 regulator-name = "vdd_cpu"; 402 regulator-min-microvolt = <800000>; 403 regulator-max-microvolt = <1430000>; 404 regulator-ramp-delay = <8000>; 405 vin-supply = <&vdd_sys>; 406 }; 407 }; 408 409 &pinctrl { 410 pcfg_output_high: pcfg-output-high { 411 output-high; 412 }; 413 414 emmc { 415 /* 416 * We run eMMC at max speed; bump up drive strength. 417 * We also have external pulls, so disable the internal ones. 418 */ 419 emmc_clk: emmc-clk { 420 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>; 421 }; 422 423 emmc_cmd: emmc-cmd { 424 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>; 425 }; 426 427 emmc_bus8: emmc-bus8 { 428 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>, 429 <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 430 <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>, 431 <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>, 432 <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>, 433 <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>, 434 <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>, 435 <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>; 436 }; 437 }; 438 439 gmac { 440 phy_int: phy-int { 441 rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>; 442 }; 443 444 phy_rst: phy-rst { 445 rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; 446 }; 447 }; 448 449 leds { 450 user_led: user-led { 451 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>; 452 }; 453 }; 454 455 pmic { 456 pmic_int: pmic-int { 457 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; 458 }; 459 460 /* Pin for switching state between sleep and non-sleep state */ 461 pmic_sleep: pmic-sleep { 462 rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>; 463 }; 464 }; 465 }; 466 467 &pwm1 { 468 status = "okay"; 469 }; 470 471 &saradc { 472 status = "okay"; 473 vref-supply = <&vdd_1v8_ldo>; 474 }; 475 476 &spi2 { 477 status = "okay"; 478 479 serial_flash: flash@0 { 480 compatible = "micron,n25q128a13", "jedec,spi-nor"; 481 reg = <0x0>; 482 spi-max-frequency = <50000000>; 483 m25p,fast-read; 484 #address-cells = <1>; 485 #size-cells = <1>; 486 status = "okay"; 487 }; 488 }; 489 490 &tsadc { 491 status = "okay"; 492 rockchip,hw-tshut-mode = <0>; 493 rockchip,hw-tshut-polarity = <0>; 494 }; 495 496 &vopb { 497 status = "okay"; 498 }; 499 500 &vopb_mmu { 501 status = "okay"; 502 }; 503 504 &vopl { 505 status = "okay"; 506 }; 507 508 &vopl_mmu { 509 status = "okay"; 510 }; 511 512 &wdt { 513 status = "okay"; 514 }; 515
