1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #include <dt-bindings/gpio/gpio.h> 4 #include <dt-bindings/interrupt-controller/irq.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/pinctrl/rockchip.h> 7 #include <dt-bindings/clock/rk3288-cru.h> 8 #include <dt-bindings/power-domain/rk3288.h> 9 #include <dt-bindings/thermal/thermal.h> 10 #include <dt-bindings/video/rk3288.h> 11 #include "skeleton.dtsi" 12 13 / { 14 compatible = "rockchip,rk3288"; 15 16 interrupt-parent = <&gic>; 17 aliases { 18 gpio0 = &gpio0; 19 gpio1 = &gpio1; 20 gpio2 = &gpio2; 21 gpio3 = &gpio3; 22 gpio4 = &gpio4; 23 gpio5 = &gpio5; 24 gpio6 = &gpio6; 25 gpio7 = &gpio7; 26 gpio8 = &gpio8; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 i2c4 = &i2c4; 32 i2c5 = &i2c5; 33 mmc0 = &emmc; 34 mmc1 = &sdmmc; 35 mmc2 = &sdio0; 36 mmc3 = &sdio1; 37 mshc0 = &emmc; 38 mshc1 = &sdmmc; 39 mshc2 = &sdio0; 40 mshc3 = &sdio1; 41 serial0 = &uart0; 42 serial1 = &uart1; 43 serial2 = &uart2; 44 serial3 = &uart3; 45 serial4 = &uart4; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi2 = &spi2; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 enable-method = "rockchip,rk3066-smp"; 55 rockchip,pmu = <&pmu>; 56 57 cpu0: cpu@500 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a12"; 60 reg = <0x500>; 61 operating-points = < 62 /* KHz uV */ 63 1800000 1400000 64 1704000 1350000 65 1608000 1300000 66 1512000 1250000 67 1416000 1200000 68 1200000 1100000 69 1008000 1050000 70 816000 1000000 71 696000 950000 72 600000 900000 73 408000 900000 74 216000 900000 75 126000 900000 76 >; 77 #cooling-cells = <2>; /* min followed by max */ 78 clock-latency = <40000>; 79 clocks = <&cru ARMCLK>; 80 resets = <&cru SRST_CORE0>; 81 }; 82 cpu@501 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a12"; 85 reg = <0x501>; 86 resets = <&cru SRST_CORE1>; 87 }; 88 cpu@502 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a12"; 91 reg = <0x502>; 92 resets = <&cru SRST_CORE2>; 93 }; 94 cpu@503 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a12"; 97 reg = <0x503>; 98 resets = <&cru SRST_CORE3>; 99 }; 100 }; 101 102 amba { 103 compatible = "arm,amba-bus"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges; 107 108 dmac_peri: dma-controller@ff250000 { 109 compatible = "arm,pl330", "arm,primecell"; 110 broken-no-flushp; 111 reg = <0xff250000 0x4000>; 112 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 114 #dma-cells = <1>; 115 clocks = <&cru ACLK_DMAC2>; 116 clock-names = "apb_pclk"; 117 }; 118 119 dmac_bus_ns: dma-controller@ff600000 { 120 compatible = "arm,pl330", "arm,primecell"; 121 broken-no-flushp; 122 reg = <0xff600000 0x4000>; 123 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 125 #dma-cells = <1>; 126 clocks = <&cru ACLK_DMAC1>; 127 clock-names = "apb_pclk"; 128 status = "disabled"; 129 }; 130 131 dmac_bus_s: dma-controller@ffb20000 { 132 compatible = "arm,pl330", "arm,primecell"; 133 broken-no-flushp; 134 reg = <0xffb20000 0x4000>; 135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 137 #dma-cells = <1>; 138 clocks = <&cru ACLK_DMAC1>; 139 clock-names = "apb_pclk"; 140 }; 141 }; 142 143 xin24m: oscillator { 144 compatible = "fixed-clock"; 145 clock-frequency = <24000000>; 146 clock-output-names = "xin24m"; 147 #clock-cells = <0>; 148 }; 149 150 timer { 151 arm,use-physical-timer; 152 compatible = "arm,armv7-timer"; 153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 157 clock-frequency = <24000000>; 158 always-on; 159 }; 160 161 display-subsystem { 162 compatible = "rockchip,display-subsystem"; 163 ports = <&vopl_out>, <&vopb_out>; 164 }; 165 166 sdmmc: dwmmc@ff0c0000 { 167 compatible = "rockchip,rk3288-dw-mshc"; 168 max-frequency = <150000000>; 169 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 170 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 171 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 172 fifo-depth = <0x100>; 173 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 174 reg = <0xff0c0000 0x4000>; 175 status = "disabled"; 176 }; 177 178 sdio0: dwmmc@ff0d0000 { 179 compatible = "rockchip,rk3288-dw-mshc"; 180 max-frequency = <150000000>; 181 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 182 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 183 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 184 fifo-depth = <0x100>; 185 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 186 reg = <0xff0d0000 0x4000>; 187 status = "disabled"; 188 }; 189 190 sdio1: dwmmc@ff0e0000 { 191 compatible = "rockchip,rk3288-dw-mshc"; 192 max-frequency = <150000000>; 193 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 194 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 195 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 196 fifo-depth = <0x100>; 197 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 198 reg = <0xff0e0000 0x4000>; 199 status = "disabled"; 200 }; 201 202 emmc: dwmmc@ff0f0000 { 203 compatible = "rockchip,rk3288-dw-mshc"; 204 max-frequency = <150000000>; 205 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 206 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 207 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 208 fifo-depth = <0x100>; 209 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 210 reg = <0xff0f0000 0x4000>; 211 status = "disabled"; 212 }; 213 214 saradc: saradc@ff100000 { 215 compatible = "rockchip,saradc"; 216 reg = <0xff100000 0x100>; 217 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 218 #io-channel-cells = <1>; 219 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 220 clock-names = "saradc", "apb_pclk"; 221 status = "disabled"; 222 }; 223 224 spi0: spi@ff110000 { 225 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 226 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 227 clock-names = "spiclk", "apb_pclk"; 228 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 229 dma-names = "tx", "rx"; 230 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 233 reg = <0xff110000 0x1000>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 status = "disabled"; 237 }; 238 239 spi1: spi@ff120000 { 240 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 241 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 242 clock-names = "spiclk", "apb_pclk"; 243 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 244 dma-names = "tx", "rx"; 245 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 248 reg = <0xff120000 0x1000>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 status = "disabled"; 252 }; 253 254 spi2: spi@ff130000 { 255 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 256 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 257 clock-names = "spiclk", "apb_pclk"; 258 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 259 dma-names = "tx", "rx"; 260 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 263 reg = <0xff130000 0x1000>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 status = "disabled"; 267 }; 268 269 i2c1: i2c@ff140000 { 270 compatible = "rockchip,rk3288-i2c"; 271 reg = <0xff140000 0x1000>; 272 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 clock-names = "i2c"; 276 clocks = <&cru PCLK_I2C1>; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&i2c1_xfer>; 279 status = "disabled"; 280 }; 281 282 i2c3: i2c@ff150000 { 283 compatible = "rockchip,rk3288-i2c"; 284 reg = <0xff150000 0x1000>; 285 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 clock-names = "i2c"; 289 clocks = <&cru PCLK_I2C3>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&i2c3_xfer>; 292 status = "disabled"; 293 }; 294 295 i2c4: i2c@ff160000 { 296 compatible = "rockchip,rk3288-i2c"; 297 reg = <0xff160000 0x1000>; 298 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 clock-names = "i2c"; 302 clocks = <&cru PCLK_I2C4>; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&i2c4_xfer>; 305 status = "disabled"; 306 }; 307 308 i2c5: i2c@ff170000 { 309 compatible = "rockchip,rk3288-i2c"; 310 reg = <0xff170000 0x1000>; 311 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 clock-names = "i2c"; 315 clocks = <&cru PCLK_I2C5>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&i2c5_xfer>; 318 status = "disabled"; 319 }; 320 uart0: serial@ff180000 { 321 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 322 reg = <0xff180000 0x100>; 323 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 324 reg-shift = <2>; 325 reg-io-width = <4>; 326 clock-frequency = <24000000>; 327 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 328 clock-names = "baudclk", "apb_pclk"; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&uart0_xfer>; 331 status = "disabled"; 332 }; 333 334 uart1: serial@ff190000 { 335 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 336 reg = <0xff190000 0x100>; 337 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 338 reg-shift = <2>; 339 reg-io-width = <4>; 340 clock-frequency = <24000000>; 341 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 342 clock-names = "baudclk", "apb_pclk"; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&uart1_xfer>; 345 status = "disabled"; 346 }; 347 348 uart2: serial@ff690000 { 349 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 350 reg = <0xff690000 0x100>; 351 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 352 reg-shift = <2>; 353 reg-io-width = <4>; 354 clock-frequency = <24000000>; 355 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 356 clock-names = "baudclk", "apb_pclk"; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&uart2_xfer>; 359 status = "disabled"; 360 }; 361 uart3: serial@ff1b0000 { 362 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 363 reg = <0xff1b0000 0x100>; 364 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 365 reg-shift = <2>; 366 reg-io-width = <4>; 367 clock-frequency = <24000000>; 368 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 369 clock-names = "baudclk", "apb_pclk"; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&uart3_xfer>; 372 status = "disabled"; 373 }; 374 375 uart4: serial@ff1c0000 { 376 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 377 reg = <0xff1c0000 0x100>; 378 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 379 reg-shift = <2>; 380 reg-io-width = <4>; 381 clock-frequency = <24000000>; 382 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 383 clock-names = "baudclk", "apb_pclk"; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&uart4_xfer>; 386 status = "disabled"; 387 }; 388 thermal: thermal-zones { 389 #include "rk3288-thermal.dtsi" 390 }; 391 392 tsadc: tsadc@ff280000 { 393 compatible = "rockchip,rk3288-tsadc"; 394 reg = <0xff280000 0x100>; 395 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 397 clock-names = "tsadc", "apb_pclk"; 398 resets = <&cru SRST_TSADC>; 399 reset-names = "tsadc-apb"; 400 pinctrl-names = "otp_out"; 401 pinctrl-0 = <&otp_out>; 402 #thermal-sensor-cells = <1>; 403 hw-shut-temp = <125000>; 404 status = "disabled"; 405 }; 406 407 gmac: ethernet@ff290000 { 408 compatible = "rockchip,rk3288-gmac"; 409 reg = <0xff290000 0x10000>; 410 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 411 interrupt-names = "macirq"; 412 rockchip,grf = <&grf>; 413 clocks = <&cru SCLK_MAC>, 414 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 415 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 416 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 417 clock-names = "stmmaceth", 418 "mac_clk_rx", "mac_clk_tx", 419 "clk_mac_ref", "clk_mac_refout", 420 "aclk_mac", "pclk_mac"; 421 }; 422 423 usb_host0_ehci: usb@ff500000 { 424 compatible = "generic-ehci"; 425 reg = <0xff500000 0x100>; 426 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&cru HCLK_USBHOST0>; 428 clock-names = "usbhost"; 429 phys = <&usbphy1>; 430 phy-names = "usb"; 431 status = "disabled"; 432 }; 433 434 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 435 436 usb_host1: usb@ff540000 { 437 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 438 "snps,dwc2"; 439 reg = <0xff540000 0x40000>; 440 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&cru HCLK_USBHOST1>; 442 clock-names = "otg"; 443 phys = <&usbphy2>; 444 phy-names = "usb2-phy"; 445 status = "disabled"; 446 }; 447 448 usb_otg: usb@ff580000 { 449 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 450 "snps,dwc2"; 451 reg = <0xff580000 0x40000>; 452 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cru HCLK_OTG0>; 454 clock-names = "otg"; 455 dr_mode = "otg"; 456 phys = <&usbphy0>; 457 phy-names = "usb2-phy"; 458 status = "disabled"; 459 }; 460 461 usb_hsic: usb@ff5c0000 { 462 compatible = "generic-ehci"; 463 reg = <0xff5c0000 0x100>; 464 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&cru HCLK_HSIC>; 466 clock-names = "usbhost"; 467 status = "disabled"; 468 }; 469 470 dmc: dmc@ff610000 { 471 u-boot,dm-pre-reloc; 472 compatible = "rockchip,rk3288-dmc", "syscon"; 473 rockchip,cru = <&cru>; 474 rockchip,grf = <&grf>; 475 rockchip,pmu = <&pmu>; 476 rockchip,sgrf = <&sgrf>; 477 rockchip,noc = <&noc>; 478 reg = <0xff610000 0x3fc 479 0xff620000 0x294 480 0xff630000 0x3fc 481 0xff640000 0x294>; 482 rockchip,sram = <&ddr_sram>; 483 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, 484 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, 485 <&cru ARMCLK>; 486 clock-names = "pclk_ddrupctl0", "pclk_publ0", 487 "pclk_ddrupctl1", "pclk_publ1", 488 "arm_clk"; 489 }; 490 491 i2c0: i2c@ff650000 { 492 compatible = "rockchip,rk3288-i2c"; 493 reg = <0xff650000 0x1000>; 494 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 clock-names = "i2c"; 498 clocks = <&cru PCLK_I2C0>; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&i2c0_xfer>; 501 status = "disabled"; 502 }; 503 504 i2c2: i2c@ff660000 { 505 compatible = "rockchip,rk3288-i2c"; 506 reg = <0xff660000 0x1000>; 507 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 clock-names = "i2c"; 511 clocks = <&cru PCLK_I2C2>; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&i2c2_xfer>; 514 status = "disabled"; 515 }; 516 517 pwm0: pwm@ff680000 { 518 compatible = "rockchip,rk3288-pwm"; 519 reg = <0xff680000 0x10>; 520 #pwm-cells = <3>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&pwm0_pin>; 523 clocks = <&cru PCLK_PWM>; 524 clock-names = "pwm"; 525 rockchip,grf = <&grf>; 526 status = "disabled"; 527 }; 528 529 pwm1: pwm@ff680010 { 530 compatible = "rockchip,rk3288-pwm"; 531 reg = <0xff680010 0x10>; 532 #pwm-cells = <3>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&pwm1_pin>; 535 clocks = <&cru PCLK_PWM>; 536 clock-names = "pwm"; 537 rockchip,grf = <&grf>; 538 status = "disabled"; 539 }; 540 541 pwm2: pwm@ff680020 { 542 compatible = "rockchip,rk3288-pwm"; 543 reg = <0xff680020 0x10>; 544 #pwm-cells = <3>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&pwm2_pin>; 547 clocks = <&cru PCLK_PWM>; 548 clock-names = "pwm"; 549 rockchip,grf = <&grf>; 550 status = "disabled"; 551 }; 552 553 pwm3: pwm@ff680030 { 554 compatible = "rockchip,rk3288-pwm"; 555 reg = <0xff680030 0x10>; 556 #pwm-cells = <2>; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&pwm3_pin>; 559 clocks = <&cru PCLK_PWM>; 560 clock-names = "pwm"; 561 rockchip,grf = <&grf>; 562 status = "disabled"; 563 }; 564 565 bus_intmem@ff700000 { 566 compatible = "mmio-sram"; 567 reg = <0xff700000 0x18000>; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 ranges = <0 0xff700000 0x18000>; 571 smp-sram@0 { 572 compatible = "rockchip,rk3066-smp-sram"; 573 reg = <0x00 0x10>; 574 }; 575 ddr_sram: ddr-sram@1000 { 576 compatible = "rockchip,rk3288-ddr-sram"; 577 reg = <0x1000 0x4000>; 578 }; 579 }; 580 581 sram@ff720000 { 582 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 583 reg = <0xff720000 0x1000>; 584 }; 585 586 pmu: power-management@ff730000 { 587 u-boot,dm-pre-reloc; 588 compatible = "rockchip,rk3288-pmu", "syscon"; 589 reg = <0xff730000 0x100>; 590 }; 591 592 sgrf: syscon@ff740000 { 593 u-boot,dm-pre-reloc; 594 compatible = "rockchip,rk3288-sgrf", "syscon"; 595 reg = <0xff740000 0x1000>; 596 }; 597 598 cru: clock-controller@ff760000 { 599 compatible = "rockchip,rk3288-cru"; 600 reg = <0xff760000 0x1000>; 601 rockchip,grf = <&grf>; 602 u-boot,dm-pre-reloc; 603 #clock-cells = <1>; 604 #reset-cells = <1>; 605 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 606 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 607 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 608 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 609 <&cru PCLK_PERI>; 610 assigned-clock-rates = <594000000>, <400000000>, 611 <500000000>, <300000000>, 612 <150000000>, <75000000>, 613 <300000000>, <150000000>, 614 <75000000>; 615 }; 616 617 grf: syscon@ff770000 { 618 u-boot,dm-pre-reloc; 619 compatible = "rockchip,rk3288-grf", "syscon"; 620 reg = <0xff770000 0x1000>; 621 }; 622 623 wdt: watchdog@ff800000 { 624 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 625 reg = <0xff800000 0x100>; 626 clocks = <&cru PCLK_WDT>; 627 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 628 status = "disabled"; 629 }; 630 631 spdif: sound@ff88b0000 { 632 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 633 reg = <0xff8b0000 0x10000>; 634 #sound-dai-cells = <0>; 635 clock-names = "hclk", "mclk"; 636 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; 637 dmas = <&dmac_bus_s 3>; 638 dma-names = "tx"; 639 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&spdif_tx>; 642 rockchip,grf = <&grf>; 643 status = "disabled"; 644 }; 645 646 i2s: i2s@ff890000 { 647 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 648 reg = <0xff890000 0x10000>; 649 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 653 dma-names = "tx", "rx"; 654 clock-names = "i2s_hclk", "i2s_clk"; 655 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&i2s0_bus>; 658 status = "disabled"; 659 }; 660 661 vopb: vop@ff930000 { 662 u-boot,dm-pre-reloc; 663 compatible = "rockchip,rk3288-vop"; 664 reg = <0xff930000 0x19c>; 665 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 667 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 668 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 669 reset-names = "axi", "ahb", "dclk"; 670 iommus = <&vopb_mmu>; 671 power-domains = <&power RK3288_PD_VIO>; 672 status = "disabled"; 673 vopb_out: port { 674 #address-cells = <1>; 675 #size-cells = <0>; 676 vopb_out_edp: endpoint@0 { 677 reg = <0>; 678 remote-endpoint = <&edp_in_vopb>; 679 }; 680 vopb_out_hdmi: endpoint@1 { 681 reg = <1>; 682 remote-endpoint = <&hdmi_in_vopb>; 683 }; 684 vopb_out_lvds: endpoint@2 { 685 reg = <2>; 686 remote-endpoint = <&lvds_in_vopb>; 687 }; 688 vopb_out_mipi: endpoint@3 { 689 reg = <3>; 690 remote-endpoint = <&mipi_in_vopb>; 691 }; 692 693 }; 694 }; 695 696 vopb_mmu: iommu@ff930300 { 697 compatible = "rockchip,iommu"; 698 reg = <0xff930300 0x100>; 699 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 700 interrupt-names = "vopb_mmu"; 701 power-domains = <&power RK3288_PD_VIO>; 702 #iommu-cells = <0>; 703 status = "disabled"; 704 }; 705 706 vopl: vop@ff940000 { 707 compatible = "rockchip,rk3288-vop"; 708 reg = <0xff940000 0x19c>; 709 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 711 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 712 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 713 reset-names = "axi", "ahb", "dclk"; 714 iommus = <&vopl_mmu>; 715 power-domains = <&power RK3288_PD_VIO>; 716 status = "disabled"; 717 u-boot,dm-pre-reloc; 718 vopl_out: port { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 vopl_out_edp: endpoint@0 { 722 reg = <0>; 723 remote-endpoint = <&edp_in_vopl>; 724 }; 725 vopl_out_hdmi: endpoint@1 { 726 reg = <1>; 727 remote-endpoint = <&hdmi_in_vopl>; 728 }; 729 vopl_out_lvds: endpoint@2 { 730 reg = <2>; 731 remote-endpoint = <&lvds_in_vopl>; 732 }; 733 vopl_out_mipi: endpoint@3 { 734 reg = <3>; 735 remote-endpoint = <&mipi_in_vopl>; 736 }; 737 738 }; 739 }; 740 741 vopl_mmu: iommu@ff940300 { 742 compatible = "rockchip,iommu"; 743 reg = <0xff940300 0x100>; 744 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 745 interrupt-names = "vopl_mmu"; 746 power-domains = <&power RK3288_PD_VIO>; 747 #iommu-cells = <0>; 748 status = "disabled"; 749 }; 750 751 edp: edp@ff970000 { 752 compatible = "rockchip,rk3288-edp"; 753 reg = <0xff970000 0x4000>; 754 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; 756 rockchip,grf = <&grf>; 757 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; 758 resets = <&cru 111>; 759 reset-names = "edp"; 760 power-domains = <&power RK3288_PD_VIO>; 761 status = "disabled"; 762 ports { 763 edp_in: port { 764 #address-cells = <1>; 765 #size-cells = <0>; 766 edp_in_vopb: endpoint@0 { 767 reg = <0>; 768 remote-endpoint = <&vopb_out_edp>; 769 }; 770 edp_in_vopl: endpoint@1 { 771 reg = <1>; 772 remote-endpoint = <&vopl_out_edp>; 773 }; 774 }; 775 }; 776 }; 777 778 hdmi: hdmi@ff980000 { 779 compatible = "rockchip,rk3288-dw-hdmi"; 780 reg = <0xff980000 0x20000>; 781 reg-io-width = <4>; 782 ddc-i2c-bus = <&i2c5>; 783 rockchip,grf = <&grf>; 784 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; 786 clock-names = "iahb", "isfr"; 787 status = "disabled"; 788 ports { 789 hdmi_in: port { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 hdmi_in_vopb: endpoint@0 { 793 reg = <0>; 794 remote-endpoint = <&vopb_out_hdmi>; 795 }; 796 hdmi_in_vopl: endpoint@1 { 797 reg = <1>; 798 remote-endpoint = <&vopl_out_hdmi>; 799 }; 800 }; 801 }; 802 }; 803 804 lvds: lvds@ff96c000 { 805 compatible = "rockchip,rk3288-lvds"; 806 reg = <0xff96c000 0x4000>; 807 clocks = <&cru PCLK_LVDS_PHY>; 808 clock-names = "pclk_lvds"; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&lcdc0_ctl>; 811 rockchip,grf = <&grf>; 812 status = "disabled"; 813 ports { 814 #address-cells = <1>; 815 #size-cells = <0>; 816 lvds_in: port@0 { 817 reg = <0>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 lvds_in_vopb: endpoint@0 { 821 reg = <0>; 822 remote-endpoint = <&vopb_out_lvds>; 823 }; 824 lvds_in_vopl: endpoint@1 { 825 reg = <1>; 826 remote-endpoint = <&vopl_out_lvds>; 827 }; 828 }; 829 }; 830 }; 831 832 mipi_dsi0: mipi@ff960000 { 833 compatible = "rockchip,rk3288_mipi_dsi"; 834 reg = <0xff960000 0x4000>; 835 clocks = <&cru PCLK_MIPI_DSI0>; 836 clock-names = "pclk_mipi"; 837 /*pinctrl-names = "default"; 838 pinctrl-0 = <&lcdc0_ctl>;*/ 839 rockchip,grf = <&grf>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 status = "disabled"; 843 ports { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 reg = <1>; 847 mipi_in: port { 848 #address-cells = <1>; 849 #size-cells = <0>; 850 mipi_in_vopb: endpoint@0 { 851 reg = <0>; 852 remote-endpoint = <&vopb_out_mipi>; 853 }; 854 mipi_in_vopl: endpoint@1 { 855 reg = <1>; 856 remote-endpoint = <&vopl_out_mipi>; 857 }; 858 }; 859 }; 860 }; 861 862 hdmi_audio: hdmi_audio { 863 compatible = "rockchip,rk3288-hdmi-audio"; 864 i2s-controller = <&i2s>; 865 status = "disable"; 866 }; 867 868 vpu: video-codec@ff9a0000 { 869 compatible = "rockchip,rk3288-vpu"; 870 reg = <0xff9a0000 0x800>; 871 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "vepu", "vdpu"; 874 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 875 clock-names = "aclk_vcodec", "hclk_vcodec"; 876 power-domains = <&power RK3288_PD_VIDEO>; 877 iommus = <&vpu_mmu>; 878 }; 879 880 vpu_mmu: iommu@ff9a0800 { 881 compatible = "rockchip,iommu"; 882 reg = <0xff9a0800 0x100>; 883 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 884 interrupt-names = "vpu_mmu"; 885 power-domains = <&power RK3288_PD_VIDEO>; 886 #iommu-cells = <0>; 887 }; 888 889 gpu: gpu@ffa30000 { 890 compatible = "arm,malit764", 891 "arm,malit76x", 892 "arm,malit7xx", 893 "arm,mali-midgard"; 894 reg = <0xffa30000 0x10000>; 895 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 898 interrupt-names = "JOB", "MMU", "GPU"; 899 clocks = <&cru ACLK_GPU>; 900 clock-names = "aclk_gpu"; 901 operating-points = < 902 /* KHz uV */ 903 100000 950000 904 200000 950000 905 300000 1000000 906 400000 1100000 907 /* 500000 1200000 - See crosbug.com/p/33857 */ 908 600000 1250000 909 >; 910 power-domains = <&power RK3288_PD_GPU>; 911 status = "disabled"; 912 }; 913 914 noc: syscon@ffac0000 { 915 u-boot,dm-pre-reloc; 916 compatible = "rockchip,rk3288-noc", "syscon"; 917 reg = <0xffac0000 0x2000>; 918 }; 919 920 efuse: efuse@ffb40000 { 921 compatible = "rockchip,rk3288-efuse"; 922 reg = <0xffb40000 0x10000>; 923 status = "disabled"; 924 }; 925 926 gic: interrupt-controller@ffc01000 { 927 compatible = "arm,gic-400"; 928 interrupt-controller; 929 #interrupt-cells = <3>; 930 #address-cells = <0>; 931 932 reg = <0xffc01000 0x1000>, 933 <0xffc02000 0x1000>, 934 <0xffc04000 0x2000>, 935 <0xffc06000 0x2000>; 936 interrupts = <GIC_PPI 9 0xf04>; 937 }; 938 939 cpuidle: cpuidle { 940 compatible = "rockchip,rk3288-cpuidle"; 941 }; 942 943 usbphy: phy { 944 compatible = "rockchip,rk3288-usb-phy"; 945 rockchip,grf = <&grf>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 status = "disabled"; 949 950 usbphy0: usb-phy0 { 951 #phy-cells = <0>; 952 reg = <0x320>; 953 clocks = <&cru SCLK_OTGPHY0>; 954 clock-names = "phyclk"; 955 }; 956 957 usbphy1: usb-phy1 { 958 #phy-cells = <0>; 959 reg = <0x334>; 960 clocks = <&cru SCLK_OTGPHY1>; 961 clock-names = "phyclk"; 962 }; 963 964 usbphy2: usb-phy2 { 965 #phy-cells = <0>; 966 reg = <0x348>; 967 clocks = <&cru SCLK_OTGPHY2>; 968 clock-names = "phyclk"; 969 }; 970 }; 971 972 pinctrl: pinctrl { 973 compatible = "rockchip,rk3288-pinctrl"; 974 rockchip,grf = <&grf>; 975 rockchip,pmu = <&pmu>; 976 #address-cells = <1>; 977 #size-cells = <1>; 978 ranges; 979 980 gpio0: gpio0@ff750000 { 981 compatible = "rockchip,gpio-bank"; 982 reg = <0xff750000 0x100>; 983 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&cru PCLK_GPIO0>; 985 986 gpio-controller; 987 #gpio-cells = <2>; 988 989 interrupt-controller; 990 #interrupt-cells = <2>; 991 }; 992 993 gpio1: gpio1@ff780000 { 994 compatible = "rockchip,gpio-bank"; 995 reg = <0xff780000 0x100>; 996 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&cru PCLK_GPIO1>; 998 999 gpio-controller; 1000 #gpio-cells = <2>; 1001 1002 interrupt-controller; 1003 #interrupt-cells = <2>; 1004 }; 1005 1006 gpio2: gpio2@ff790000 { 1007 compatible = "rockchip,gpio-bank"; 1008 reg = <0xff790000 0x100>; 1009 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&cru PCLK_GPIO2>; 1011 1012 gpio-controller; 1013 #gpio-cells = <2>; 1014 1015 interrupt-controller; 1016 #interrupt-cells = <2>; 1017 }; 1018 1019 gpio3: gpio3@ff7a0000 { 1020 compatible = "rockchip,gpio-bank"; 1021 reg = <0xff7a0000 0x100>; 1022 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cru PCLK_GPIO3>; 1024 1025 gpio-controller; 1026 #gpio-cells = <2>; 1027 1028 interrupt-controller; 1029 #interrupt-cells = <2>; 1030 }; 1031 1032 gpio4: gpio4@ff7b0000 { 1033 compatible = "rockchip,gpio-bank"; 1034 reg = <0xff7b0000 0x100>; 1035 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&cru PCLK_GPIO4>; 1037 1038 gpio-controller; 1039 #gpio-cells = <2>; 1040 1041 interrupt-controller; 1042 #interrupt-cells = <2>; 1043 }; 1044 1045 gpio5: gpio5@ff7c0000 { 1046 compatible = "rockchip,gpio-bank"; 1047 reg = <0xff7c0000 0x100>; 1048 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&cru PCLK_GPIO5>; 1050 1051 gpio-controller; 1052 #gpio-cells = <2>; 1053 1054 interrupt-controller; 1055 #interrupt-cells = <2>; 1056 }; 1057 1058 gpio6: gpio6@ff7d0000 { 1059 compatible = "rockchip,gpio-bank"; 1060 reg = <0xff7d0000 0x100>; 1061 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&cru PCLK_GPIO6>; 1063 1064 gpio-controller; 1065 #gpio-cells = <2>; 1066 1067 interrupt-controller; 1068 #interrupt-cells = <2>; 1069 }; 1070 1071 gpio7: gpio7@ff7e0000 { 1072 compatible = "rockchip,gpio-bank"; 1073 reg = <0xff7e0000 0x100>; 1074 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&cru PCLK_GPIO7>; 1076 1077 gpio-controller; 1078 #gpio-cells = <2>; 1079 1080 interrupt-controller; 1081 #interrupt-cells = <2>; 1082 }; 1083 1084 gpio8: gpio8@ff7f0000 { 1085 compatible = "rockchip,gpio-bank"; 1086 reg = <0xff7f0000 0x100>; 1087 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1088 clocks = <&cru PCLK_GPIO8>; 1089 1090 gpio-controller; 1091 #gpio-cells = <2>; 1092 1093 interrupt-controller; 1094 #interrupt-cells = <2>; 1095 }; 1096 1097 pcfg_pull_up: pcfg-pull-up { 1098 bias-pull-up; 1099 }; 1100 1101 pcfg_pull_down: pcfg-pull-down { 1102 bias-pull-down; 1103 }; 1104 1105 pcfg_pull_none: pcfg-pull-none { 1106 bias-disable; 1107 }; 1108 1109 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1110 bias-disable; 1111 drive-strength = <12>; 1112 }; 1113 1114 sleep { 1115 global_pwroff: global-pwroff { 1116 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; 1117 }; 1118 1119 ddrio_pwroff: ddrio-pwroff { 1120 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1121 }; 1122 1123 ddr0_retention: ddr0-retention { 1124 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; 1125 }; 1126 1127 ddr1_retention: ddr1-retention { 1128 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; 1129 }; 1130 }; 1131 1132 i2c0 { 1133 i2c0_xfer: i2c0-xfer { 1134 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 1135 <0 16 RK_FUNC_1 &pcfg_pull_none>; 1136 }; 1137 }; 1138 1139 i2c1 { 1140 i2c1_xfer: i2c1-xfer { 1141 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, 1142 <8 5 RK_FUNC_1 &pcfg_pull_none>; 1143 }; 1144 }; 1145 1146 i2c2 { 1147 i2c2_xfer: i2c2-xfer { 1148 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, 1149 <6 10 RK_FUNC_1 &pcfg_pull_none>; 1150 }; 1151 }; 1152 1153 i2c3 { 1154 i2c3_xfer: i2c3-xfer { 1155 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, 1156 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1157 }; 1158 }; 1159 1160 i2c4 { 1161 i2c4_xfer: i2c4-xfer { 1162 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, 1163 <7 18 RK_FUNC_1 &pcfg_pull_none>; 1164 }; 1165 }; 1166 1167 i2c5 { 1168 i2c5_xfer: i2c5-xfer { 1169 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, 1170 <7 20 RK_FUNC_1 &pcfg_pull_none>; 1171 }; 1172 }; 1173 1174 i2s0 { 1175 i2s0_bus: i2s0-bus { 1176 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, 1177 <6 1 RK_FUNC_1 &pcfg_pull_none>, 1178 <6 2 RK_FUNC_1 &pcfg_pull_none>, 1179 <6 3 RK_FUNC_1 &pcfg_pull_none>, 1180 <6 4 RK_FUNC_1 &pcfg_pull_none>, 1181 <6 8 RK_FUNC_1 &pcfg_pull_none>; 1182 }; 1183 }; 1184 1185 lcdc0 { 1186 lcdc0_ctl: lcdc0-ctl { 1187 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, 1188 <1 25 RK_FUNC_1 &pcfg_pull_none>, 1189 <1 26 RK_FUNC_1 &pcfg_pull_none>, 1190 <1 27 RK_FUNC_1 &pcfg_pull_none>; 1191 }; 1192 }; 1193 1194 sdmmc { 1195 sdmmc_clk: sdmmc-clk { 1196 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 1197 }; 1198 1199 sdmmc_cmd: sdmmc-cmd { 1200 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; 1201 }; 1202 1203 sdmmc_cd: sdmcc-cd { 1204 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; 1205 }; 1206 1207 sdmmc_bus1: sdmmc-bus1 { 1208 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; 1209 }; 1210 1211 sdmmc_bus4: sdmmc-bus4 { 1212 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, 1213 <6 17 RK_FUNC_1 &pcfg_pull_up>, 1214 <6 18 RK_FUNC_1 &pcfg_pull_up>, 1215 <6 19 RK_FUNC_1 &pcfg_pull_up>; 1216 }; 1217 }; 1218 1219 sdio0 { 1220 sdio0_bus1: sdio0-bus1 { 1221 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; 1222 }; 1223 1224 sdio0_bus4: sdio0-bus4 { 1225 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, 1226 <4 21 RK_FUNC_1 &pcfg_pull_up>, 1227 <4 22 RK_FUNC_1 &pcfg_pull_up>, 1228 <4 23 RK_FUNC_1 &pcfg_pull_up>; 1229 }; 1230 1231 sdio0_cmd: sdio0-cmd { 1232 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; 1233 }; 1234 1235 sdio0_clk: sdio0-clk { 1236 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; 1237 }; 1238 1239 sdio0_cd: sdio0-cd { 1240 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; 1241 }; 1242 1243 sdio0_wp: sdio0-wp { 1244 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; 1245 }; 1246 1247 sdio0_pwr: sdio0-pwr { 1248 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; 1249 }; 1250 1251 sdio0_bkpwr: sdio0-bkpwr { 1252 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; 1253 }; 1254 1255 sdio0_int: sdio0-int { 1256 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; 1257 }; 1258 }; 1259 1260 sdio1 { 1261 sdio1_bus1: sdio1-bus1 { 1262 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>; 1263 }; 1264 1265 sdio1_bus4: sdio1-bus4 { 1266 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>, 1267 <3 25 RK_FUNC_4 &pcfg_pull_up>, 1268 <3 26 RK_FUNC_4 &pcfg_pull_up>, 1269 <3 27 RK_FUNC_4 &pcfg_pull_up>; 1270 }; 1271 1272 sdio1_cd: sdio1-cd { 1273 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>; 1274 }; 1275 1276 sdio1_wp: sdio1-wp { 1277 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>; 1278 }; 1279 1280 sdio1_bkpwr: sdio1-bkpwr { 1281 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>; 1282 }; 1283 1284 sdio1_int: sdio1-int { 1285 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>; 1286 }; 1287 1288 sdio1_cmd: sdio1-cmd { 1289 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>; 1290 }; 1291 1292 sdio1_clk: sdio1-clk { 1293 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>; 1294 }; 1295 1296 sdio1_pwr: sdio1-pwr { 1297 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>; 1298 }; 1299 }; 1300 1301 emmc { 1302 emmc_clk: emmc-clk { 1303 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 1304 }; 1305 1306 emmc_cmd: emmc-cmd { 1307 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; 1308 }; 1309 1310 emmc_pwr: emmc-pwr { 1311 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; 1312 }; 1313 1314 emmc_bus1: emmc-bus1 { 1315 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; 1316 }; 1317 1318 emmc_bus4: emmc-bus4 { 1319 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1320 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1321 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1322 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1323 }; 1324 1325 emmc_bus8: emmc-bus8 { 1326 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1327 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1328 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1329 <3 3 RK_FUNC_2 &pcfg_pull_up>, 1330 <3 4 RK_FUNC_2 &pcfg_pull_up>, 1331 <3 5 RK_FUNC_2 &pcfg_pull_up>, 1332 <3 6 RK_FUNC_2 &pcfg_pull_up>, 1333 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1334 }; 1335 }; 1336 1337 spi0 { 1338 spi0_clk: spi0-clk { 1339 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; 1340 }; 1341 spi0_cs0: spi0-cs0 { 1342 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; 1343 }; 1344 spi0_tx: spi0-tx { 1345 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; 1346 }; 1347 spi0_rx: spi0-rx { 1348 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; 1349 }; 1350 spi0_cs1: spi0-cs1 { 1351 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; 1352 }; 1353 }; 1354 spi1 { 1355 spi1_clk: spi1-clk { 1356 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; 1357 }; 1358 spi1_cs0: spi1-cs0 { 1359 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; 1360 }; 1361 spi1_rx: spi1-rx { 1362 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; 1363 }; 1364 spi1_tx: spi1-tx { 1365 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; 1366 }; 1367 }; 1368 1369 spi2 { 1370 spi2_cs1: spi2-cs1 { 1371 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; 1372 }; 1373 spi2_clk: spi2-clk { 1374 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; 1375 }; 1376 spi2_cs0: spi2-cs0 { 1377 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; 1378 }; 1379 spi2_rx: spi2-rx { 1380 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; 1381 }; 1382 spi2_tx: spi2-tx { 1383 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; 1384 }; 1385 }; 1386 1387 uart0 { 1388 uart0_xfer: uart0-xfer { 1389 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 1390 <4 17 RK_FUNC_1 &pcfg_pull_none>; 1391 }; 1392 1393 uart0_cts: uart0-cts { 1394 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; 1395 }; 1396 1397 uart0_rts: uart0-rts { 1398 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; 1399 }; 1400 }; 1401 1402 uart1 { 1403 uart1_xfer: uart1-xfer { 1404 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, 1405 <5 9 RK_FUNC_1 &pcfg_pull_none>; 1406 }; 1407 1408 uart1_cts: uart1-cts { 1409 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; 1410 }; 1411 1412 uart1_rts: uart1-rts { 1413 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; 1414 }; 1415 }; 1416 1417 uart2 { 1418 uart2_xfer: uart2-xfer { 1419 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, 1420 <7 23 RK_FUNC_1 &pcfg_pull_none>; 1421 }; 1422 /* no rts / cts for uart2 */ 1423 }; 1424 1425 uart3 { 1426 uart3_xfer: uart3-xfer { 1427 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, 1428 <7 8 RK_FUNC_1 &pcfg_pull_none>; 1429 }; 1430 1431 uart3_cts: uart3-cts { 1432 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; 1433 }; 1434 1435 uart3_rts: uart3-rts { 1436 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; 1437 }; 1438 }; 1439 1440 uart4 { 1441 uart4_xfer: uart4-xfer { 1442 rockchip,pins = <5 12 3 &pcfg_pull_up>, 1443 <5 13 3 &pcfg_pull_none>; 1444 }; 1445 1446 uart4_cts: uart4-cts { 1447 rockchip,pins = <5 14 3 &pcfg_pull_none>; 1448 }; 1449 1450 uart4_rts: uart4-rts { 1451 rockchip,pins = <5 15 3 &pcfg_pull_none>; 1452 }; 1453 }; 1454 1455 tsadc { 1456 otp_out: otp-out { 1457 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 1458 }; 1459 }; 1460 1461 pwm0 { 1462 pwm0_pin: pwm0-pin { 1463 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1464 }; 1465 }; 1466 1467 pwm1 { 1468 pwm1_pin: pwm1-pin { 1469 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; 1470 }; 1471 }; 1472 1473 pwm2 { 1474 pwm2_pin: pwm2-pin { 1475 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>; 1476 }; 1477 }; 1478 1479 pwm3 { 1480 pwm3_pin: pwm3-pin { 1481 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>; 1482 }; 1483 }; 1484 1485 gmac { 1486 rgmii_pins: rgmii-pins { 1487 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1488 <3 31 3 &pcfg_pull_none>, 1489 <3 26 3 &pcfg_pull_none>, 1490 <3 27 3 &pcfg_pull_none>, 1491 <3 28 3 &pcfg_pull_none_12ma>, 1492 <3 29 3 &pcfg_pull_none_12ma>, 1493 <3 24 3 &pcfg_pull_none_12ma>, 1494 <3 25 3 &pcfg_pull_none_12ma>, 1495 <4 0 3 &pcfg_pull_none>, 1496 <4 5 3 &pcfg_pull_none>, 1497 <4 6 3 &pcfg_pull_none>, 1498 <4 9 3 &pcfg_pull_none_12ma>, 1499 <4 4 3 &pcfg_pull_none_12ma>, 1500 <4 1 3 &pcfg_pull_none>, 1501 <4 3 3 &pcfg_pull_none>; 1502 }; 1503 1504 rmii_pins: rmii-pins { 1505 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1506 <3 31 3 &pcfg_pull_none>, 1507 <3 28 3 &pcfg_pull_none>, 1508 <3 29 3 &pcfg_pull_none>, 1509 <4 0 3 &pcfg_pull_none>, 1510 <4 5 3 &pcfg_pull_none>, 1511 <4 4 3 &pcfg_pull_none>, 1512 <4 1 3 &pcfg_pull_none>, 1513 <4 2 3 &pcfg_pull_none>, 1514 <4 3 3 &pcfg_pull_none>; 1515 }; 1516 }; 1517 1518 spdif { 1519 spdif_tx: spdif-tx { 1520 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; 1521 }; 1522 }; 1523 }; 1524 1525 power: power-controller { 1526 compatible = "rockchip,rk3288-power-controller"; 1527 #power-domain-cells = <1>; 1528 rockchip,pmu = <&pmu>; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 1532 pd_gpu { 1533 reg = <RK3288_PD_GPU>; 1534 clocks = <&cru ACLK_GPU>; 1535 }; 1536 1537 pd_hevc { 1538 reg = <RK3288_PD_HEVC>; 1539 clocks = <&cru ACLK_HEVC>, 1540 <&cru SCLK_HEVC_CABAC>, 1541 <&cru SCLK_HEVC_CORE>, 1542 <&cru HCLK_HEVC>; 1543 }; 1544 1545 pd_vio { 1546 reg = <RK3288_PD_VIO>; 1547 clocks = <&cru ACLK_IEP>, 1548 <&cru ACLK_ISP>, 1549 <&cru ACLK_RGA>, 1550 <&cru ACLK_VIP>, 1551 <&cru ACLK_VOP0>, 1552 <&cru ACLK_VOP1>, 1553 <&cru DCLK_VOP0>, 1554 <&cru DCLK_VOP1>, 1555 <&cru HCLK_IEP>, 1556 <&cru HCLK_ISP>, 1557 <&cru HCLK_RGA>, 1558 <&cru HCLK_VIP>, 1559 <&cru HCLK_VOP0>, 1560 <&cru HCLK_VOP1>, 1561 <&cru PCLK_EDP_CTRL>, 1562 <&cru PCLK_HDMI_CTRL>, 1563 <&cru PCLK_LVDS_PHY>, 1564 <&cru PCLK_MIPI_CSI>, 1565 <&cru PCLK_MIPI_DSI0>, 1566 <&cru PCLK_MIPI_DSI1>, 1567 <&cru SCLK_EDP_24M>, 1568 <&cru SCLK_EDP>, 1569 <&cru SCLK_HDMI_CEC>, 1570 <&cru SCLK_HDMI_HDCP>, 1571 <&cru SCLK_ISP_JPE>, 1572 <&cru SCLK_ISP>, 1573 <&cru SCLK_RGA>; 1574 }; 1575 1576 pd_video { 1577 reg = <RK3288_PD_VIDEO>; 1578 clocks = <&cru ACLK_VCODEC>, 1579 <&cru HCLK_VCODEC>; 1580 }; 1581 }; 1582 }; 1583
