1 // SPDX-License-Identifier: GPL-2.0+ OR X11 2 /* 3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 4 */ 5 6 /dts-v1/; 7 #include "rk3368.dtsi" 8 #include "rk3368-lion-u-boot.dtsi" 9 #include <dt-bindings/input/input.h> 10 11 / { 12 model = "Theobroma Systems RK3368-uQ7 SoM"; 13 compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368"; 14 15 aliases { 16 mmc0 = &emmc; 17 mmc1 = &sdmmc; 18 }; 19 20 memory@0 { 21 device_type = "memory"; 22 reg = <0x0 0x0 0x0 0x80000000>; 23 }; 24 25 ext_gmac: gmac-clk { 26 compatible = "fixed-clock"; 27 clock-frequency = <125000000>; 28 clock-output-names = "ext_gmac"; 29 #clock-cells = <0>; 30 }; 31 32 vcc_sys: vcc-sys-regulator { 33 compatible = "regulator-fixed"; 34 regulator-name = "vcc_sys"; 35 regulator-min-microvolt = <5000000>; 36 regulator-max-microvolt = <5000000>; 37 regulator-always-on; 38 regulator-boot-on; 39 }; 40 }; 41 42 &uart0 { 43 status = "okay"; 44 }; 45 46 &emmc { 47 status = "okay"; 48 bus-width = <8>; 49 cap-mmc-highspeed; 50 clock-frequency = <150000000>; 51 disable-wp; 52 keep-power-in-suspend; 53 non-removable; 54 num-slots = <1>; 55 vmmc-supply = <&vcc33_io>; 56 vqmmc-supply = <&vcc18_io>; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; 59 }; 60 61 &sdmmc { 62 status = "okay"; 63 }; 64 65 &gmac { 66 status = "okay"; 67 phy-supply = <&vcc33_io>; 68 phy-mode = "rgmii"; 69 clock_in_out = "input"; 70 snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; 71 snps,reset-active-low; 72 snps,reset-delays-us = <2 10000 50000>; 73 assigned-clocks = <&cru SCLK_MAC>; 74 assigned-clock-parents = <&ext_gmac>; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&rgmii_pins>; 77 tx_delay = <0x10>; 78 rx_delay = <0x10>; 79 }; 80 81 &i2c0 { 82 status = "okay"; 83 84 rk808: pmic@1b { 85 compatible = "rockchip,rk808"; 86 reg = <0x1b>; 87 interrupt-parent = <&gpio0>; 88 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 89 rockchip,system-power-controller; 90 vcc1-supply = <&vcc_sys>; 91 vcc2-supply = <&vcc_sys>; 92 vcc3-supply = <&vcc_sys>; 93 vcc4-supply = <&vcc_sys>; 94 vcc6-supply = <&vcc_sys>; 95 vcc7-supply = <&vcc_sys>; 96 vcc8-supply = <&vcc_sys>; 97 vcc9-supply = <&vcc_sys>; 98 vcc10-supply = <&vcc_sys>; 99 vcc11-supply = <&vcc_sys>; 100 vcc12-supply = <&vcc_sys>; 101 clock-output-names = "xin32k", "rk808-clkout2"; 102 #clock-cells = <1>; 103 104 regulators { 105 vdd_cpu: DCDC_REG1 { 106 regulator-always-on; 107 regulator-boot-on; 108 regulator-min-microvolt = <700000>; 109 regulator-max-microvolt = <1500000>; 110 regulator-name = "vdd_cpu"; 111 }; 112 113 vdd_log: DCDC_REG2 { 114 regulator-always-on; 115 regulator-boot-on; 116 regulator-min-microvolt = <700000>; 117 regulator-max-microvolt = <1500000>; 118 regulator-name = "vdd_log"; 119 }; 120 121 vcc_ddr: DCDC_REG3 { 122 regulator-always-on; 123 regulator-boot-on; 124 regulator-name = "vcc_ddr"; 125 }; 126 127 vcc33_io: DCDC_REG4 { 128 regulator-always-on; 129 regulator-boot-on; 130 regulator-min-microvolt = <3300000>; 131 regulator-max-microvolt = <3300000>; 132 regulator-name = "vcc33_io"; 133 }; 134 135 vcc33_video: LDO_REG2 { 136 regulator-always-on; 137 regulator-boot-on; 138 regulator-min-microvolt = <3300000>; 139 regulator-max-microvolt = <3300000>; 140 regulator-name = "vcc33_video"; 141 }; 142 143 vdd10_pll: LDO_REG3 { 144 regulator-always-on; 145 regulator-boot-on; 146 regulator-min-microvolt = <1000000>; 147 regulator-max-microvolt = <1000000>; 148 regulator-name = "vdd10_pll"; 149 }; 150 151 vcc18_io: LDO_REG4 { 152 regulator-boot-on; 153 regulator-min-microvolt = <1800000>; 154 regulator-max-microvolt = <1800000>; 155 regulator-name = "vcc18_io"; 156 }; 157 158 vdd10_video: LDO_REG6 { 159 regulator-always-on; 160 regulator-boot-on; 161 regulator-min-microvolt = <1000000>; 162 regulator-max-microvolt = <1000000>; 163 regulator-name = "vdd10_video"; 164 }; 165 166 vcc18_video: LDO_REG8 { 167 regulator-always-on; 168 regulator-boot-on; 169 regulator-min-microvolt = <1800000>; 170 regulator-max-microvolt = <1800000>; 171 regulator-name = "vcc18_video"; 172 }; 173 }; 174 }; 175 }; 176 177 &uart0 { 178 status = "okay"; 179 }; 180 181 &spi1 { 182 status = "okay"; 183 184 #address-cells = <1>; 185 #size-cells = <0>; 186 187 spiflash: w25q32dw@0 { 188 compatible = "spi-flash"; 189 reg = <0>; 190 spi-max-frequency = <49500000>; 191 spi-cpol; 192 spi-cpha; 193 }; 194 }; 195
