1 // SPDX-License-Identifier: GPL-2.0+ OR X11 2 /* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko (a] sntech.de> 5 */ 6 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include "skeleton.dtsi" 10 11 / { 12 interrupt-parent = <&gic>; 13 14 aliases { 15 ethernet0 = &emac; 16 i2c0 = &i2c0; 17 i2c1 = &i2c1; 18 i2c2 = &i2c2; 19 i2c3 = &i2c3; 20 i2c4 = &i2c4; 21 mshc0 = &emmc; 22 mshc1 = &mmc0; 23 mshc2 = &mmc1; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 serial3 = &uart3; 28 spi0 = &spi0; 29 spi1 = &spi1; 30 }; 31 32 amba { 33 compatible = "simple-bus"; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 ranges; 37 38 dmac1_s: dma-controller@20018000 { 39 compatible = "arm,pl330", "arm,primecell"; 40 reg = <0x20018000 0x4000>; 41 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 43 #dma-cells = <1>; 44 arm,pl330-broken-no-flushp; 45 clocks = <&cru ACLK_DMA1>; 46 clock-names = "apb_pclk"; 47 }; 48 49 dmac1_ns: dma-controller@2001c000 { 50 compatible = "arm,pl330", "arm,primecell"; 51 reg = <0x2001c000 0x4000>; 52 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 54 #dma-cells = <1>; 55 arm,pl330-broken-no-flushp; 56 clocks = <&cru ACLK_DMA1>; 57 clock-names = "apb_pclk"; 58 status = "disabled"; 59 }; 60 61 dmac2: dma-controller@20078000 { 62 compatible = "arm,pl330", "arm,primecell"; 63 reg = <0x20078000 0x4000>; 64 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 66 #dma-cells = <1>; 67 arm,pl330-broken-no-flushp; 68 clocks = <&cru ACLK_DMA2>; 69 clock-names = "apb_pclk"; 70 }; 71 }; 72 73 xin24m: oscillator { 74 compatible = "fixed-clock"; 75 clock-frequency = <24000000>; 76 #clock-cells = <0>; 77 clock-output-names = "xin24m"; 78 }; 79 80 L2: l2-cache-controller@10138000 { 81 compatible = "arm,pl310-cache"; 82 reg = <0x10138000 0x1000>; 83 cache-unified; 84 cache-level = <2>; 85 }; 86 87 scu@1013c000 { 88 compatible = "arm,cortex-a9-scu"; 89 reg = <0x1013c000 0x100>; 90 }; 91 92 global_timer: global-timer@1013c200 { 93 compatible = "arm,cortex-a9-global-timer"; 94 reg = <0x1013c200 0x20>; 95 interrupts = <GIC_PPI 11 0x304>; 96 clocks = <&cru CORE_PERI>; 97 }; 98 99 local_timer: local-timer@1013c600 { 100 compatible = "arm,cortex-a9-twd-timer"; 101 reg = <0x1013c600 0x20>; 102 interrupts = <GIC_PPI 13 0x304>; 103 clocks = <&cru CORE_PERI>; 104 }; 105 106 gic: interrupt-controller@1013d000 { 107 compatible = "arm,cortex-a9-gic"; 108 interrupt-controller; 109 #interrupt-cells = <3>; 110 reg = <0x1013d000 0x1000>, 111 <0x1013c100 0x0100>; 112 }; 113 114 uart0: serial@10124000 { 115 compatible = "snps,dw-apb-uart"; 116 reg = <0x10124000 0x400>; 117 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 118 reg-shift = <2>; 119 reg-io-width = <1>; 120 clock-names = "baudclk", "apb_pclk"; 121 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 122 status = "disabled"; 123 }; 124 125 uart1: serial@10126000 { 126 compatible = "snps,dw-apb-uart"; 127 reg = <0x10126000 0x400>; 128 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 129 reg-shift = <2>; 130 reg-io-width = <1>; 131 clock-names = "baudclk", "apb_pclk"; 132 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 133 status = "disabled"; 134 }; 135 136 noc: syscon@10128000 { 137 u-boot,dm-spl; 138 compatible = "rockchip,rk3188-noc", "syscon"; 139 reg = <0x10128000 0x2000>; 140 }; 141 142 usb_otg: usb@10180000 { 143 compatible = "rockchip,rk3066-usb", "snps,dwc2"; 144 reg = <0x10180000 0x40000>; 145 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&cru HCLK_OTG0>; 147 clock-names = "otg"; 148 dr_mode = "otg"; 149 g-np-tx-fifo-size = <16>; 150 g-rx-fifo-size = <275>; 151 g-tx-fifo-size = <256 128 128 64 64 32>; 152 g-use-dma; 153 phys = <&usbphy0>; 154 phy-names = "usb2-phy"; 155 status = "disabled"; 156 }; 157 158 usb_host: usb@101c0000 { 159 compatible = "snps,dwc2"; 160 reg = <0x101c0000 0x40000>; 161 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&cru HCLK_OTG1>; 163 clock-names = "otg"; 164 dr_mode = "host"; 165 phys = <&usbphy1>; 166 phy-names = "usb2-phy"; 167 status = "disabled"; 168 }; 169 170 emac: ethernet@10204000 { 171 compatible = "snps,arc-emac"; 172 reg = <0x10204000 0x3c>; 173 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 177 rockchip,grf = <&grf>; 178 179 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; 180 clock-names = "hclk", "macref"; 181 max-speed = <100>; 182 phy-mode = "rmii"; 183 184 status = "disabled"; 185 }; 186 187 mmc0: dwmmc@10214000 { 188 compatible = "rockchip,rk2928-dw-mshc"; 189 reg = <0x10214000 0x1000>; 190 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 192 clock-names = "biu", "ciu"; 193 fifo-depth = <256>; 194 status = "disabled"; 195 }; 196 197 mmc1: dwmmc@10218000 { 198 compatible = "rockchip,rk2928-dw-mshc"; 199 reg = <0x10218000 0x1000>; 200 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 202 clock-names = "biu", "ciu"; 203 fifo-depth = <256>; 204 status = "disabled"; 205 }; 206 207 emmc: dwmmc@1021c000 { 208 compatible = "rockchip,rk2928-dw-mshc"; 209 reg = <0x1021c000 0x1000>; 210 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 212 clock-names = "biu", "ciu"; 213 fifo-depth = <256>; 214 status = "disabled"; 215 }; 216 217 pmu: pmu@20004000 { 218 compatible = "rockchip,rk3066-pmu", "syscon"; 219 reg = <0x20004000 0x100>; 220 u-boot,dm-spl; 221 }; 222 223 grf: grf@20008000 { 224 compatible = "syscon"; 225 reg = <0x20008000 0x200>; 226 u-boot,dm-spl; 227 }; 228 229 dmc: dmc@20020000 { 230 /* unreviewed u-boot-specific binding */ 231 compatible = "rockchip,rk3188-dmc", "syscon"; 232 rockchip,cru = <&cru>; 233 rockchip,grf = <&grf>; 234 rockchip,pmu = <&pmu>; 235 rockchip,noc = <&noc>; 236 reg = <0x20020000 0x3fc 237 0x20040000 0x294>; 238 clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>; 239 clock-names = "pclk_ddrupctl", "pclk_publ"; 240 u-boot,dm-spl; 241 }; 242 243 i2c0: i2c@2002d000 { 244 compatible = "rockchip,rk3066-i2c"; 245 reg = <0x2002d000 0x1000>; 246 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 250 rockchip,grf = <&grf>; 251 252 clock-names = "i2c"; 253 clocks = <&cru PCLK_I2C0>; 254 255 status = "disabled"; 256 }; 257 258 i2c1: i2c@2002f000 { 259 compatible = "rockchip,rk3066-i2c"; 260 reg = <0x2002f000 0x1000>; 261 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 265 rockchip,grf = <&grf>; 266 267 clocks = <&cru PCLK_I2C1>; 268 clock-names = "i2c"; 269 270 status = "disabled"; 271 }; 272 273 pwm0: pwm@20030000 { 274 compatible = "rockchip,rk2928-pwm"; 275 reg = <0x20030000 0x10>; 276 #pwm-cells = <2>; 277 clocks = <&cru PCLK_PWM01>; 278 status = "disabled"; 279 }; 280 281 pwm1: pwm@20030010 { 282 compatible = "rockchip,rk2928-pwm"; 283 reg = <0x20030010 0x10>; 284 #pwm-cells = <2>; 285 clocks = <&cru PCLK_PWM01>; 286 status = "disabled"; 287 }; 288 289 wdt: watchdog@2004c000 { 290 compatible = "snps,dw-wdt"; 291 reg = <0x2004c000 0x100>; 292 clocks = <&cru PCLK_WDT>; 293 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 294 status = "disabled"; 295 }; 296 297 pwm2: pwm@20050020 { 298 compatible = "rockchip,rk2928-pwm"; 299 reg = <0x20050020 0x10>; 300 #pwm-cells = <2>; 301 clocks = <&cru PCLK_PWM23>; 302 status = "disabled"; 303 }; 304 305 pwm3: pwm@20050030 { 306 compatible = "rockchip,rk2928-pwm"; 307 reg = <0x20050030 0x10>; 308 #pwm-cells = <2>; 309 clocks = <&cru PCLK_PWM23>; 310 status = "disabled"; 311 }; 312 313 i2c2: i2c@20056000 { 314 compatible = "rockchip,rk3066-i2c"; 315 reg = <0x20056000 0x1000>; 316 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 320 rockchip,grf = <&grf>; 321 322 clocks = <&cru PCLK_I2C2>; 323 clock-names = "i2c"; 324 325 status = "disabled"; 326 }; 327 328 i2c3: i2c@2005a000 { 329 compatible = "rockchip,rk3066-i2c"; 330 reg = <0x2005a000 0x1000>; 331 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 335 rockchip,grf = <&grf>; 336 337 clocks = <&cru PCLK_I2C3>; 338 clock-names = "i2c"; 339 340 status = "disabled"; 341 }; 342 343 i2c4: i2c@2005e000 { 344 compatible = "rockchip,rk3066-i2c"; 345 reg = <0x2005e000 0x1000>; 346 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 350 rockchip,grf = <&grf>; 351 352 clocks = <&cru PCLK_I2C4>; 353 clock-names = "i2c"; 354 355 status = "disabled"; 356 }; 357 358 uart2: serial@20064000 { 359 compatible = "snps,dw-apb-uart"; 360 reg = <0x20064000 0x400>; 361 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 362 reg-shift = <2>; 363 reg-io-width = <1>; 364 clock-frequency = <24000000>; 365 clock-names = "baudclk", "apb_pclk"; 366 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 367 status = "disabled"; 368 }; 369 370 uart3: serial@20068000 { 371 compatible = "snps,dw-apb-uart"; 372 reg = <0x20068000 0x400>; 373 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 374 reg-shift = <2>; 375 reg-io-width = <1>; 376 clock-names = "baudclk", "apb_pclk"; 377 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 378 status = "disabled"; 379 }; 380 381 saradc: saradc@2006c000 { 382 compatible = "rockchip,saradc"; 383 reg = <0x2006c000 0x100>; 384 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 385 #io-channel-cells = <1>; 386 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 387 clock-names = "saradc", "apb_pclk"; 388 status = "disabled"; 389 }; 390 391 spi0: spi@20070000 { 392 compatible = "rockchip,rk3066-spi"; 393 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 394 clock-names = "spiclk", "apb_pclk"; 395 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 396 reg = <0x20070000 0x1000>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 dmas = <&dmac2 10>, <&dmac2 11>; 400 dma-names = "tx", "rx"; 401 status = "disabled"; 402 }; 403 404 spi1: spi@20074000 { 405 compatible = "rockchip,rk3066-spi"; 406 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 407 clock-names = "spiclk", "apb_pclk"; 408 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 409 reg = <0x20074000 0x1000>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 dmas = <&dmac2 12>, <&dmac2 13>; 413 dma-names = "tx", "rx"; 414 status = "disabled"; 415 }; 416 }; 417
