1 #ifndef _ST_PINCFG_H_ 2 #define _ST_PINCFG_H_ 3 4 /* Alternate functions */ 5 #define ALT1 1 6 #define ALT2 2 7 #define ALT3 3 8 #define ALT4 4 9 #define ALT5 5 10 #define ALT6 6 11 #define ALT7 7 12 13 /* Output enable */ 14 #define OE (1 << 27) 15 /* Pull Up */ 16 #define PU (1 << 26) 17 /* Open Drain */ 18 #define OD (1 << 25) 19 #define RT (1 << 23) 20 #define INVERTCLK (1 << 22) 21 #define CLKNOTDATA (1 << 21) 22 #define DOUBLE_EDGE (1 << 20) 23 #define CLK_A (0 << 18) 24 #define CLK_B (1 << 18) 25 #define CLK_C (2 << 18) 26 #define CLK_D (3 << 18) 27 28 /* User-frendly defines for Pin Direction */ 29 /* oe = 0, pu = 0, od = 0 */ 30 #define IN (0) 31 /* oe = 0, pu = 1, od = 0 */ 32 #define IN_PU (PU) 33 /* oe = 1, pu = 0, od = 0 */ 34 #define OUT (OE) 35 /* oe = 1, pu = 0, od = 1 */ 36 #define BIDIR (OE | OD) 37 /* oe = 1, pu = 1, od = 1 */ 38 #define BIDIR_PU (OE | PU | OD) 39 40 /* RETIME_TYPE */ 41 /* 42 * B Mode 43 * Bypass retime with optional delay parameter 44 */ 45 #define BYPASS (0) 46 /* 47 * R0, R1, R0D, R1D modes 48 * single-edge data non inverted clock, retime data with clk 49 */ 50 #define SE_NICLK_IO (RT) 51 /* 52 * RIV0, RIV1, RIV0D, RIV1D modes 53 * single-edge data inverted clock, retime data with clk 54 */ 55 #define SE_ICLK_IO (RT | INVERTCLK) 56 /* 57 * R0E, R1E, R0ED, R1ED modes 58 * double-edge data, retime data with clk 59 */ 60 #define DE_IO (RT | DOUBLE_EDGE) 61 /* 62 * CIV0, CIV1 modes with inverted clock 63 * Retiming the clk pins will park clock & reduce the noise within the core. 64 */ 65 #define ICLK (RT | CLKNOTDATA | INVERTCLK) 66 /* 67 * CLK0, CLK1 modes with non-inverted clock 68 * Retiming the clk pins will park clock & reduce the noise within the core. 69 */ 70 #define NICLK (RT | CLKNOTDATA) 71 #endif /* _ST_PINCFG_H_ */ 72
