1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 6 /* STM32MP157C ED1 and ED2 BOARD configuration 7 * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. 8 * Reference used NT5CC256M16DP-DI from NANYA 9 * 10 * DDR type / Platform DDR3/3L 11 * freq 533MHz 12 * width 32 13 * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G 14 * DDR density 8 15 * timing mode optimized 16 * Scheduling/QoS options : type = 2 17 * address mapping : RBC 18 */ 19 20 #define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36" 21 #define DDR_MEM_SPEED 533 22 #define DDR_MEM_SIZE 0x40000000 23 24 #define DDR_MSTR 0x00040401 25 #define DDR_MRCTRL0 0x00000010 26 #define DDR_MRCTRL1 0x00000000 27 #define DDR_DERATEEN 0x00000000 28 #define DDR_DERATEINT 0x00800000 29 #define DDR_PWRCTL 0x00000000 30 #define DDR_PWRTMG 0x00400010 31 #define DDR_HWLPCTL 0x00000000 32 #define DDR_RFSHCTL0 0x00210000 33 #define DDR_RFSHCTL3 0x00000000 34 #define DDR_RFSHTMG 0x0081008B 35 #define DDR_CRCPARCTL0 0x00000000 36 #define DDR_DRAMTMG0 0x121B2414 37 #define DDR_DRAMTMG1 0x000A041C 38 #define DDR_DRAMTMG2 0x0608090F 39 #define DDR_DRAMTMG3 0x0050400C 40 #define DDR_DRAMTMG4 0x08040608 41 #define DDR_DRAMTMG5 0x06060403 42 #define DDR_DRAMTMG6 0x02020002 43 #define DDR_DRAMTMG7 0x00000202 44 #define DDR_DRAMTMG8 0x00001005 45 #define DDR_DRAMTMG14 0x000000A0 46 #define DDR_ZQCTL0 0xC2000040 47 #define DDR_DFITMG0 0x02060105 48 #define DDR_DFITMG1 0x00000202 49 #define DDR_DFILPCFG0 0x07000000 50 #define DDR_DFIUPD0 0xC0400003 51 #define DDR_DFIUPD1 0x00000000 52 #define DDR_DFIUPD2 0x00000000 53 #define DDR_DFIPHYMSTR 0x00000000 54 #define DDR_ADDRMAP1 0x00080808 55 #define DDR_ADDRMAP2 0x00000000 56 #define DDR_ADDRMAP3 0x00000000 57 #define DDR_ADDRMAP4 0x00001F1F 58 #define DDR_ADDRMAP5 0x07070707 59 #define DDR_ADDRMAP6 0x0F070707 60 #define DDR_ADDRMAP9 0x00000000 61 #define DDR_ADDRMAP10 0x00000000 62 #define DDR_ADDRMAP11 0x00000000 63 #define DDR_ODTCFG 0x06000600 64 #define DDR_ODTMAP 0x00000001 65 #define DDR_SCHED 0x00001201 66 #define DDR_SCHED1 0x00000000 67 #define DDR_PERFHPR1 0x01000001 68 #define DDR_PERFLPR1 0x08000200 69 #define DDR_PERFWR1 0x08000400 70 #define DDR_DBG0 0x00000000 71 #define DDR_DBG1 0x00000000 72 #define DDR_DBGCMD 0x00000000 73 #define DDR_POISONCFG 0x00000000 74 #define DDR_PCCFG 0x00000010 75 #define DDR_PCFGR_0 0x00010000 76 #define DDR_PCFGW_0 0x00000000 77 #define DDR_PCFGQOS0_0 0x02100B03 78 #define DDR_PCFGQOS1_0 0x00800100 79 #define DDR_PCFGWQOS0_0 0x01100B03 80 #define DDR_PCFGWQOS1_0 0x01000200 81 #define DDR_PCFGR_1 0x00010000 82 #define DDR_PCFGW_1 0x00000000 83 #define DDR_PCFGQOS0_1 0x02100B03 84 #define DDR_PCFGQOS1_1 0x00800100 85 #define DDR_PCFGWQOS0_1 0x01100B03 86 #define DDR_PCFGWQOS1_1 0x01000200 87 #define DDR_PGCR 0x01442E02 88 #define DDR_PTR0 0x0022AA5B 89 #define DDR_PTR1 0x04841104 90 #define DDR_PTR2 0x042DA068 91 #define DDR_ACIOCR 0x10400812 92 #define DDR_DXCCR 0x00000C40 93 #define DDR_DSGCR 0xF200001F 94 #define DDR_DCR 0x0000000B 95 #define DDR_DTPR0 0x38D488D0 96 #define DDR_DTPR1 0x098B00D8 97 #define DDR_DTPR2 0x10023600 98 #define DDR_MR0 0x00000840 99 #define DDR_MR1 0x00000000 100 #define DDR_MR2 0x00000208 101 #define DDR_MR3 0x00000000 102 #define DDR_ODTCR 0x00010000 103 #define DDR_ZQ0CR1 0x0000005B 104 #define DDR_DX0GCR 0x0000CE81 105 #define DDR_DX0DLLCR 0x40000000 106 #define DDR_DX0DQTR 0xFFFFFFFF 107 #define DDR_DX0DQSTR 0x3DB02000 108 #define DDR_DX1GCR 0x0000CE81 109 #define DDR_DX1DLLCR 0x40000000 110 #define DDR_DX1DQTR 0xFFFFFFFF 111 #define DDR_DX1DQSTR 0x3DB02000 112 #define DDR_DX2GCR 0x0000CE81 113 #define DDR_DX2DLLCR 0x40000000 114 #define DDR_DX2DQTR 0xFFFFFFFF 115 #define DDR_DX2DQSTR 0x3DB02000 116 #define DDR_DX3GCR 0x0000CE81 117 #define DDR_DX3DLLCR 0x40000000 118 #define DDR_DX3DQTR 0xFFFFFFFF 119 #define DDR_DX3DQSTR 0x3DB02000 120 121 #include "stm32mp15-ddr.dtsi" 122
