1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 // 3 // Device Tree Source for UniPhier LD20 SoC 4 // 5 // Copyright (C) 2015-2016 Socionext Inc. 6 // Author: Masahiro Yamada <yamada.masahiro (a] socionext.com> 7 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/thermal/thermal.h> 11 12 /memreserve/ 0x80000000 0x02000000; 13 14 / { 15 compatible = "socionext,uniphier-ld20"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&gic>; 19 20 cpus { 21 #address-cells = <2>; 22 #size-cells = <0>; 23 24 cpu-map { 25 cluster0 { 26 core0 { 27 cpu = <&cpu0>; 28 }; 29 core1 { 30 cpu = <&cpu1>; 31 }; 32 }; 33 34 cluster1 { 35 core0 { 36 cpu = <&cpu2>; 37 }; 38 core1 { 39 cpu = <&cpu3>; 40 }; 41 }; 42 }; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a72", "arm,armv8"; 47 reg = <0 0x000>; 48 clocks = <&sys_clk 32>; 49 enable-method = "psci"; 50 operating-points-v2 = <&cluster0_opp>; 51 #cooling-cells = <2>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a72", "arm,armv8"; 57 reg = <0 0x001>; 58 clocks = <&sys_clk 32>; 59 enable-method = "psci"; 60 operating-points-v2 = <&cluster0_opp>; 61 }; 62 63 cpu2: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53", "arm,armv8"; 66 reg = <0 0x100>; 67 clocks = <&sys_clk 33>; 68 enable-method = "psci"; 69 operating-points-v2 = <&cluster1_opp>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu3: cpu@101 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53", "arm,armv8"; 76 reg = <0 0x101>; 77 clocks = <&sys_clk 33>; 78 enable-method = "psci"; 79 operating-points-v2 = <&cluster1_opp>; 80 }; 81 }; 82 83 cluster0_opp: opp-table0 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-250000000 { 88 opp-hz = /bits/ 64 <250000000>; 89 clock-latency-ns = <300>; 90 }; 91 opp-275000000 { 92 opp-hz = /bits/ 64 <275000000>; 93 clock-latency-ns = <300>; 94 }; 95 opp-500000000 { 96 opp-hz = /bits/ 64 <500000000>; 97 clock-latency-ns = <300>; 98 }; 99 opp-550000000 { 100 opp-hz = /bits/ 64 <550000000>; 101 clock-latency-ns = <300>; 102 }; 103 opp-666667000 { 104 opp-hz = /bits/ 64 <666667000>; 105 clock-latency-ns = <300>; 106 }; 107 opp-733334000 { 108 opp-hz = /bits/ 64 <733334000>; 109 clock-latency-ns = <300>; 110 }; 111 opp-1000000000 { 112 opp-hz = /bits/ 64 <1000000000>; 113 clock-latency-ns = <300>; 114 }; 115 opp-1100000000 { 116 opp-hz = /bits/ 64 <1100000000>; 117 clock-latency-ns = <300>; 118 }; 119 }; 120 121 cluster1_opp: opp-table1 { 122 compatible = "operating-points-v2"; 123 opp-shared; 124 125 opp-250000000 { 126 opp-hz = /bits/ 64 <250000000>; 127 clock-latency-ns = <300>; 128 }; 129 opp-275000000 { 130 opp-hz = /bits/ 64 <275000000>; 131 clock-latency-ns = <300>; 132 }; 133 opp-500000000 { 134 opp-hz = /bits/ 64 <500000000>; 135 clock-latency-ns = <300>; 136 }; 137 opp-550000000 { 138 opp-hz = /bits/ 64 <550000000>; 139 clock-latency-ns = <300>; 140 }; 141 opp-666667000 { 142 opp-hz = /bits/ 64 <666667000>; 143 clock-latency-ns = <300>; 144 }; 145 opp-733334000 { 146 opp-hz = /bits/ 64 <733334000>; 147 clock-latency-ns = <300>; 148 }; 149 opp-1000000000 { 150 opp-hz = /bits/ 64 <1000000000>; 151 clock-latency-ns = <300>; 152 }; 153 opp-1100000000 { 154 opp-hz = /bits/ 64 <1100000000>; 155 clock-latency-ns = <300>; 156 }; 157 }; 158 159 psci { 160 compatible = "arm,psci-1.0"; 161 method = "smc"; 162 }; 163 164 clocks { 165 refclk: ref { 166 compatible = "fixed-clock"; 167 #clock-cells = <0>; 168 clock-frequency = <25000000>; 169 }; 170 }; 171 172 emmc_pwrseq: emmc-pwrseq { 173 compatible = "mmc-pwrseq-emmc"; 174 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 175 }; 176 177 timer { 178 compatible = "arm,armv8-timer"; 179 interrupts = <1 13 4>, 180 <1 14 4>, 181 <1 11 4>, 182 <1 10 4>; 183 }; 184 185 thermal-zones { 186 cpu-thermal { 187 polling-delay-passive = <250>; /* 250ms */ 188 polling-delay = <1000>; /* 1000ms */ 189 thermal-sensors = <&pvtctl>; 190 191 trips { 192 cpu_crit: cpu-crit { 193 temperature = <110000>; /* 110C */ 194 hysteresis = <2000>; 195 type = "critical"; 196 }; 197 cpu_alert: cpu-alert { 198 temperature = <100000>; /* 100C */ 199 hysteresis = <2000>; 200 type = "passive"; 201 }; 202 }; 203 204 cooling-maps { 205 map0 { 206 trip = <&cpu_alert>; 207 cooling-device = <&cpu0 208 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 209 }; 210 map1 { 211 trip = <&cpu_alert>; 212 cooling-device = <&cpu2 213 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 214 }; 215 }; 216 }; 217 }; 218 219 soc@0 { 220 compatible = "simple-bus"; 221 #address-cells = <1>; 222 #size-cells = <1>; 223 ranges = <0 0 0 0xffffffff>; 224 225 serial0: serial@54006800 { 226 compatible = "socionext,uniphier-uart"; 227 status = "disabled"; 228 reg = <0x54006800 0x40>; 229 interrupts = <0 33 4>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_uart0>; 232 clocks = <&peri_clk 0>; 233 resets = <&peri_rst 0>; 234 }; 235 236 serial1: serial@54006900 { 237 compatible = "socionext,uniphier-uart"; 238 status = "disabled"; 239 reg = <0x54006900 0x40>; 240 interrupts = <0 35 4>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_uart1>; 243 clocks = <&peri_clk 1>; 244 resets = <&peri_rst 1>; 245 }; 246 247 serial2: serial@54006a00 { 248 compatible = "socionext,uniphier-uart"; 249 status = "disabled"; 250 reg = <0x54006a00 0x40>; 251 interrupts = <0 37 4>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_uart2>; 254 clocks = <&peri_clk 2>; 255 resets = <&peri_rst 2>; 256 }; 257 258 serial3: serial@54006b00 { 259 compatible = "socionext,uniphier-uart"; 260 status = "disabled"; 261 reg = <0x54006b00 0x40>; 262 interrupts = <0 177 4>; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_uart3>; 265 clocks = <&peri_clk 3>; 266 resets = <&peri_rst 3>; 267 }; 268 269 gpio: gpio@55000000 { 270 compatible = "socionext,uniphier-gpio"; 271 reg = <0x55000000 0x200>; 272 interrupt-parent = <&aidet>; 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 gpio-controller; 276 #gpio-cells = <2>; 277 gpio-ranges = <&pinctrl 0 0 0>, 278 <&pinctrl 96 0 0>, 279 <&pinctrl 160 0 0>; 280 gpio-ranges-group-names = "gpio_range0", 281 "gpio_range1", 282 "gpio_range2"; 283 ngpios = <205>; 284 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 285 <21 217 3>; 286 }; 287 288 audio@56000000 { 289 compatible = "socionext,uniphier-ld20-aio"; 290 reg = <0x56000000 0x80000>; 291 interrupts = <0 144 4>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_aout1>, 294 <&pinctrl_aoutiec1>; 295 clock-names = "aio"; 296 clocks = <&sys_clk 40>; 297 reset-names = "aio"; 298 resets = <&sys_rst 40>; 299 #sound-dai-cells = <1>; 300 socionext,syscon = <&soc_glue>; 301 302 i2s_port0: port@0 { 303 i2s_hdmi: endpoint { 304 }; 305 }; 306 307 i2s_port1: port@1 { 308 i2s_pcmin2: endpoint { 309 }; 310 }; 311 312 i2s_port2: port@2 { 313 i2s_line: endpoint { 314 dai-format = "i2s"; 315 remote-endpoint = <&evea_line>; 316 }; 317 }; 318 319 i2s_port3: port@3 { 320 i2s_hpcmout1: endpoint { 321 }; 322 }; 323 324 i2s_port4: port@4 { 325 i2s_hp: endpoint { 326 dai-format = "i2s"; 327 remote-endpoint = <&evea_hp>; 328 }; 329 }; 330 331 spdif_port0: port@5 { 332 spdif_hiecout1: endpoint { 333 }; 334 }; 335 336 src_port0: port@6 { 337 i2s_epcmout2: endpoint { 338 }; 339 }; 340 341 src_port1: port@7 { 342 i2s_epcmout3: endpoint { 343 }; 344 }; 345 346 comp_spdif_port0: port@8 { 347 comp_spdif_hiecout1: endpoint { 348 }; 349 }; 350 }; 351 352 codec@57900000 { 353 compatible = "socionext,uniphier-evea"; 354 reg = <0x57900000 0x1000>; 355 clock-names = "evea", "exiv"; 356 clocks = <&sys_clk 41>, <&sys_clk 42>; 357 reset-names = "evea", "exiv", "adamv"; 358 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; 359 #sound-dai-cells = <1>; 360 361 port@0 { 362 evea_line: endpoint { 363 remote-endpoint = <&i2s_line>; 364 }; 365 }; 366 367 port@1 { 368 evea_hp: endpoint { 369 remote-endpoint = <&i2s_hp>; 370 }; 371 }; 372 }; 373 374 adamv@57920000 { 375 compatible = "socionext,uniphier-ld20-adamv", 376 "simple-mfd", "syscon"; 377 reg = <0x57920000 0x1000>; 378 379 adamv_rst: reset { 380 compatible = "socionext,uniphier-ld20-adamv-reset"; 381 #reset-cells = <1>; 382 }; 383 }; 384 385 i2c0: i2c@58780000 { 386 compatible = "socionext,uniphier-fi2c"; 387 status = "disabled"; 388 reg = <0x58780000 0x80>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 interrupts = <0 41 4>; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_i2c0>; 394 clocks = <&peri_clk 4>; 395 resets = <&peri_rst 4>; 396 clock-frequency = <100000>; 397 }; 398 399 i2c1: i2c@58781000 { 400 compatible = "socionext,uniphier-fi2c"; 401 status = "disabled"; 402 reg = <0x58781000 0x80>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 interrupts = <0 42 4>; 406 pinctrl-names = "default"; 407 pinctrl-0 = <&pinctrl_i2c1>; 408 clocks = <&peri_clk 5>; 409 resets = <&peri_rst 5>; 410 clock-frequency = <100000>; 411 }; 412 413 i2c2: i2c@58782000 { 414 compatible = "socionext,uniphier-fi2c"; 415 reg = <0x58782000 0x80>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 interrupts = <0 43 4>; 419 clocks = <&peri_clk 6>; 420 resets = <&peri_rst 6>; 421 clock-frequency = <400000>; 422 }; 423 424 i2c3: i2c@58783000 { 425 compatible = "socionext,uniphier-fi2c"; 426 status = "disabled"; 427 reg = <0x58783000 0x80>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 interrupts = <0 44 4>; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pinctrl_i2c3>; 433 clocks = <&peri_clk 7>; 434 resets = <&peri_rst 7>; 435 clock-frequency = <100000>; 436 }; 437 438 i2c4: i2c@58784000 { 439 compatible = "socionext,uniphier-fi2c"; 440 status = "disabled"; 441 reg = <0x58784000 0x80>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 interrupts = <0 45 4>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_i2c4>; 447 clocks = <&peri_clk 8>; 448 resets = <&peri_rst 8>; 449 clock-frequency = <100000>; 450 }; 451 452 i2c5: i2c@58785000 { 453 compatible = "socionext,uniphier-fi2c"; 454 reg = <0x58785000 0x80>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 interrupts = <0 25 4>; 458 clocks = <&peri_clk 9>; 459 resets = <&peri_rst 9>; 460 clock-frequency = <400000>; 461 }; 462 463 system_bus: system-bus@58c00000 { 464 compatible = "socionext,uniphier-system-bus"; 465 status = "disabled"; 466 reg = <0x58c00000 0x400>; 467 #address-cells = <2>; 468 #size-cells = <1>; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_system_bus>; 471 }; 472 473 smpctrl@59801000 { 474 compatible = "socionext,uniphier-smpctrl"; 475 reg = <0x59801000 0x400>; 476 }; 477 478 sdctrl@59810000 { 479 compatible = "socionext,uniphier-ld20-sdctrl", 480 "simple-mfd", "syscon"; 481 reg = <0x59810000 0x400>; 482 483 sd_clk: clock { 484 compatible = "socionext,uniphier-ld20-sd-clock"; 485 #clock-cells = <1>; 486 }; 487 488 sd_rst: reset { 489 compatible = "socionext,uniphier-ld20-sd-reset"; 490 #reset-cells = <1>; 491 }; 492 }; 493 494 perictrl@59820000 { 495 compatible = "socionext,uniphier-ld20-perictrl", 496 "simple-mfd", "syscon"; 497 reg = <0x59820000 0x200>; 498 499 peri_clk: clock { 500 compatible = "socionext,uniphier-ld20-peri-clock"; 501 #clock-cells = <1>; 502 }; 503 504 peri_rst: reset { 505 compatible = "socionext,uniphier-ld20-peri-reset"; 506 #reset-cells = <1>; 507 }; 508 }; 509 510 emmc: sdhc@5a000000 { 511 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 512 reg = <0x5a000000 0x400>; 513 interrupts = <0 78 4>; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&pinctrl_emmc_1v8>; 516 clocks = <&sys_clk 4>; 517 resets = <&sys_rst 4>; 518 bus-width = <8>; 519 mmc-ddr-1_8v; 520 mmc-hs200-1_8v; 521 mmc-pwrseq = <&emmc_pwrseq>; 522 cdns,phy-input-delay-legacy = <9>; 523 cdns,phy-input-delay-mmc-highspeed = <2>; 524 cdns,phy-input-delay-mmc-ddr = <3>; 525 cdns,phy-dll-delay-sdclk = <21>; 526 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 527 }; 528 529 sd: sdhc@5a400000 { 530 compatible = "socionext,uniphier-sdhc"; 531 status = "disabled"; 532 reg = <0x5a400000 0x800>; 533 interrupts = <0 76 4>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&pinctrl_sd>; 536 clocks = <&sd_clk 0>; 537 reset-names = "host"; 538 resets = <&sd_rst 0>; 539 bus-width = <4>; 540 cap-sd-highspeed; 541 }; 542 543 soc_glue: soc-glue@5f800000 { 544 compatible = "socionext,uniphier-ld20-soc-glue", 545 "simple-mfd", "syscon"; 546 reg = <0x5f800000 0x2000>; 547 548 pinctrl: pinctrl { 549 compatible = "socionext,uniphier-ld20-pinctrl"; 550 }; 551 }; 552 553 soc-glue@5f900000 { 554 compatible = "socionext,uniphier-ld20-soc-glue-debug", 555 "simple-mfd"; 556 #address-cells = <1>; 557 #size-cells = <1>; 558 ranges = <0 0x5f900000 0x2000>; 559 560 efuse@100 { 561 compatible = "socionext,uniphier-efuse"; 562 reg = <0x100 0x28>; 563 }; 564 565 efuse@200 { 566 compatible = "socionext,uniphier-efuse"; 567 reg = <0x200 0x68>; 568 }; 569 }; 570 571 aidet: aidet@5fc20000 { 572 compatible = "socionext,uniphier-ld20-aidet"; 573 reg = <0x5fc20000 0x200>; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 }; 577 578 gic: interrupt-controller@5fe00000 { 579 compatible = "arm,gic-v3"; 580 reg = <0x5fe00000 0x10000>, /* GICD */ 581 <0x5fe80000 0x80000>; /* GICR */ 582 interrupt-controller; 583 #interrupt-cells = <3>; 584 interrupts = <1 9 4>; 585 }; 586 587 sysctrl@61840000 { 588 compatible = "socionext,uniphier-ld20-sysctrl", 589 "simple-mfd", "syscon"; 590 reg = <0x61840000 0x10000>; 591 592 sys_clk: clock { 593 compatible = "socionext,uniphier-ld20-clock"; 594 #clock-cells = <1>; 595 }; 596 597 sys_rst: reset { 598 compatible = "socionext,uniphier-ld20-reset"; 599 #reset-cells = <1>; 600 }; 601 602 watchdog { 603 compatible = "socionext,uniphier-wdt"; 604 }; 605 606 pvtctl: pvtctl { 607 compatible = "socionext,uniphier-ld20-thermal"; 608 interrupts = <0 3 4>; 609 #thermal-sensor-cells = <0>; 610 socionext,tmod-calibration = <0x0f22 0x68ee>; 611 }; 612 }; 613 614 eth: ethernet@65000000 { 615 compatible = "socionext,uniphier-ld20-ave4"; 616 status = "disabled"; 617 reg = <0x65000000 0x8500>; 618 interrupts = <0 66 4>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&pinctrl_ether_rgmii>; 621 clock-names = "ether"; 622 clocks = <&sys_clk 6>; 623 reset-names = "ether"; 624 resets = <&sys_rst 6>; 625 phy-mode = "rgmii"; 626 local-mac-address = [00 00 00 00 00 00]; 627 socionext,syscon-phy-mode = <&soc_glue 0>; 628 629 mdio: mdio { 630 #address-cells = <1>; 631 #size-cells = <0>; 632 }; 633 }; 634 635 usb: usb@65b00000 { 636 compatible = "socionext,uniphier-ld20-dwc3"; 637 reg = <0x65b00000 0x1000>; 638 #address-cells = <1>; 639 #size-cells = <1>; 640 ranges; 641 pinctrl-names = "default"; 642 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, 643 <&pinctrl_usb2>, <&pinctrl_usb3>; 644 dwc3@65a00000 { 645 compatible = "snps,dwc3"; 646 reg = <0x65a00000 0x10000>; 647 interrupts = <0 134 4>; 648 dr_mode = "host"; 649 tx-fifo-resize; 650 }; 651 }; 652 653 nand: nand@68000000 { 654 compatible = "socionext,uniphier-denali-nand-v5b"; 655 status = "disabled"; 656 reg-names = "nand_data", "denali_reg"; 657 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 658 interrupts = <0 65 4>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&pinctrl_nand>; 661 clocks = <&sys_clk 2>; 662 resets = <&sys_rst 2>; 663 }; 664 }; 665 }; 666 667 #include "uniphier-pinctrl.dtsi" 668 669 &pinctrl_aout1 { 670 drive-strength = <4>; /* default: 3.5mA */ 671 672 ao1dacck { 673 pins = "AO1DACCK"; 674 drive-strength = <5>; /* 5mA */ 675 }; 676 }; 677 678 &pinctrl_aoutiec1 { 679 drive-strength = <4>; /* default: 3.5mA */ 680 681 ao1arc { 682 pins = "AO1ARC"; 683 drive-strength = <11>; /* 11mA */ 684 }; 685 }; 686
