1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * dts file for Xilinx ZynqMP ZCU102 RevA 4 * 5 * (C) Copyright 2015 - 2018, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek (a] xilinx.com> 8 */ 9 10 /dts-v1/; 11 12 #include "zynqmp.dtsi" 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/phy/phy.h> 17 18 / { 19 model = "ZynqMP ZCU102 RevA"; 20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 21 22 aliases { 23 ethernet0 = &gem3; 24 gpio0 = &gpio; 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 mmc0 = &sdhci1; 28 rtc0 = &rtc; 29 serial0 = &uart0; 30 serial1 = &uart1; 31 serial2 = &dcc; 32 spi0 = &qspi; 33 usb0 = &usb0; 34 }; 35 36 chosen { 37 bootargs = "earlycon"; 38 stdout-path = "serial0:115200n8"; 39 }; 40 41 memory@0 { 42 device_type = "memory"; 43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 44 }; 45 46 gpio-keys { 47 compatible = "gpio-keys"; 48 autorepeat; 49 sw19 { 50 label = "sw19"; 51 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 52 linux,code = <KEY_DOWN>; 53 gpio-key,wakeup; 54 autorepeat; 55 }; 56 }; 57 58 leds { 59 compatible = "gpio-leds"; 60 heartbeat_led { 61 label = "heartbeat"; 62 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 63 linux,default-trigger = "heartbeat"; 64 }; 65 }; 66 }; 67 68 &can1 { 69 status = "okay"; 70 }; 71 72 &dcc { 73 status = "okay"; 74 }; 75 76 &fpd_dma_chan1 { 77 status = "okay"; 78 }; 79 80 &fpd_dma_chan2 { 81 status = "okay"; 82 }; 83 84 &fpd_dma_chan3 { 85 status = "okay"; 86 }; 87 88 &fpd_dma_chan4 { 89 status = "okay"; 90 }; 91 92 &fpd_dma_chan5 { 93 status = "okay"; 94 }; 95 96 &fpd_dma_chan6 { 97 status = "okay"; 98 }; 99 100 &fpd_dma_chan7 { 101 status = "okay"; 102 }; 103 104 &fpd_dma_chan8 { 105 status = "okay"; 106 }; 107 108 &gem3 { 109 status = "okay"; 110 phy-handle = <&phy0>; 111 phy-mode = "rgmii-id"; 112 phy0: phy@21 { 113 reg = <21>; 114 ti,rx-internal-delay = <0x8>; 115 ti,tx-internal-delay = <0xa>; 116 ti,fifo-depth = <0x1>; 117 }; 118 }; 119 120 &gpio { 121 status = "okay"; 122 }; 123 124 &gpu { 125 status = "okay"; 126 }; 127 128 &i2c0 { 129 status = "okay"; 130 clock-frequency = <400000>; 131 132 tca6416_u97: gpio@20 { 133 compatible = "ti,tca6416"; 134 reg = <0x20>; 135 gpio-controller; 136 #gpio-cells = <2>; 137 /* 138 * IRQ not connected 139 * Lines: 140 * 0 - PS_GTR_LAN_SEL0 141 * 1 - PS_GTR_LAN_SEL1 142 * 2 - PS_GTR_LAN_SEL2 143 * 3 - PS_GTR_LAN_SEL3 144 * 4 - PCI_CLK_DIR_SEL 145 * 5 - IIC_MUX_RESET_B 146 * 6 - GEM3_EXP_RESET_B 147 * 7, 10 - 17 - not connected 148 */ 149 150 gtr_sel0 { 151 gpio-hog; 152 gpios = <0 0>; 153 output-low; /* PCIE = 0, DP = 1 */ 154 line-name = "sel0"; 155 }; 156 gtr_sel1 { 157 gpio-hog; 158 gpios = <1 0>; 159 output-high; /* PCIE = 0, DP = 1 */ 160 line-name = "sel1"; 161 }; 162 gtr_sel2 { 163 gpio-hog; 164 gpios = <2 0>; 165 output-high; /* PCIE = 0, USB0 = 1 */ 166 line-name = "sel2"; 167 }; 168 gtr_sel3 { 169 gpio-hog; 170 gpios = <3 0>; 171 output-high; /* PCIE = 0, SATA = 1 */ 172 line-name = "sel3"; 173 }; 174 }; 175 176 tca6416_u61: gpio@21 { 177 compatible = "ti,tca6416"; 178 reg = <0x21>; 179 gpio-controller; 180 #gpio-cells = <2>; 181 /* 182 * IRQ not connected 183 * Lines: 184 * 0 - VCCPSPLL_EN 185 * 1 - MGTRAVCC_EN 186 * 2 - MGTRAVTT_EN 187 * 3 - VCCPSDDRPLL_EN 188 * 4 - MIO26_PMU_INPUT_LS 189 * 5 - PL_PMBUS_ALERT 190 * 6 - PS_PMBUS_ALERT 191 * 7 - MAXIM_PMBUS_ALERT 192 * 10 - PL_DDR4_VTERM_EN 193 * 11 - PL_DDR4_VPP_2V5_EN 194 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON 195 * 13 - PS_DIMM_SUSPEND_EN 196 * 14 - PS_DDR4_VTERM_EN 197 * 15 - PS_DDR4_VPP_2V5_EN 198 * 16 - 17 - not connected 199 */ 200 }; 201 202 i2c-mux@75 { /* u60 */ 203 compatible = "nxp,pca9544"; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 reg = <0x75>; 207 i2c@0 { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 reg = <0>; 211 /* PS_PMBUS */ 212 ina226@40 { /* u76 */ 213 compatible = "ti,ina226"; 214 reg = <0x40>; 215 shunt-resistor = <5000>; 216 }; 217 ina226@41 { /* u77 */ 218 compatible = "ti,ina226"; 219 reg = <0x41>; 220 shunt-resistor = <5000>; 221 }; 222 ina226@42 { /* u78 */ 223 compatible = "ti,ina226"; 224 reg = <0x42>; 225 shunt-resistor = <5000>; 226 }; 227 ina226@43 { /* u87 */ 228 compatible = "ti,ina226"; 229 reg = <0x43>; 230 shunt-resistor = <5000>; 231 }; 232 ina226@44 { /* u85 */ 233 compatible = "ti,ina226"; 234 reg = <0x44>; 235 shunt-resistor = <5000>; 236 }; 237 ina226@45 { /* u86 */ 238 compatible = "ti,ina226"; 239 reg = <0x45>; 240 shunt-resistor = <5000>; 241 }; 242 ina226@46 { /* u93 */ 243 compatible = "ti,ina226"; 244 reg = <0x46>; 245 shunt-resistor = <5000>; 246 }; 247 ina226@47 { /* u88 */ 248 compatible = "ti,ina226"; 249 reg = <0x47>; 250 shunt-resistor = <5000>; 251 }; 252 ina226@4a { /* u15 */ 253 compatible = "ti,ina226"; 254 reg = <0x4a>; 255 shunt-resistor = <5000>; 256 }; 257 ina226@4b { /* u92 */ 258 compatible = "ti,ina226"; 259 reg = <0x4b>; 260 shunt-resistor = <5000>; 261 }; 262 }; 263 i2c@1 { 264 #address-cells = <1>; 265 #size-cells = <0>; 266 reg = <1>; 267 /* PL_PMBUS */ 268 ina226@40 { /* u79 */ 269 compatible = "ti,ina226"; 270 reg = <0x40>; 271 shunt-resistor = <2000>; 272 }; 273 ina226@41 { /* u81 */ 274 compatible = "ti,ina226"; 275 reg = <0x41>; 276 shunt-resistor = <5000>; 277 }; 278 ina226@42 { /* u80 */ 279 compatible = "ti,ina226"; 280 reg = <0x42>; 281 shunt-resistor = <5000>; 282 }; 283 ina226@43 { /* u84 */ 284 compatible = "ti,ina226"; 285 reg = <0x43>; 286 shunt-resistor = <5000>; 287 }; 288 ina226@44 { /* u16 */ 289 compatible = "ti,ina226"; 290 reg = <0x44>; 291 shunt-resistor = <5000>; 292 }; 293 ina226@45 { /* u65 */ 294 compatible = "ti,ina226"; 295 reg = <0x45>; 296 shunt-resistor = <5000>; 297 }; 298 ina226@46 { /* u74 */ 299 compatible = "ti,ina226"; 300 reg = <0x46>; 301 shunt-resistor = <5000>; 302 }; 303 ina226@47 { /* u75 */ 304 compatible = "ti,ina226"; 305 reg = <0x47>; 306 shunt-resistor = <5000>; 307 }; 308 }; 309 i2c@2 { 310 #address-cells = <1>; 311 #size-cells = <0>; 312 reg = <2>; 313 /* MAXIM_PMBUS - 00 */ 314 max15301@a { /* u46 */ 315 compatible = "maxim,max15301"; 316 reg = <0xa>; 317 }; 318 max15303@b { /* u4 */ 319 compatible = "maxim,max15303"; 320 reg = <0xb>; 321 }; 322 max15303@10 { /* u13 */ 323 compatible = "maxim,max15303"; 324 reg = <0x10>; 325 }; 326 max15301@13 { /* u47 */ 327 compatible = "maxim,max15301"; 328 reg = <0x13>; 329 }; 330 max15303@14 { /* u7 */ 331 compatible = "maxim,max15303"; 332 reg = <0x14>; 333 }; 334 max15303@15 { /* u6 */ 335 compatible = "maxim,max15303"; 336 reg = <0x15>; 337 }; 338 max15303@16 { /* u10 */ 339 compatible = "maxim,max15303"; 340 reg = <0x16>; 341 }; 342 max15303@17 { /* u9 */ 343 compatible = "maxim,max15303"; 344 reg = <0x17>; 345 }; 346 max15301@18 { /* u63 */ 347 compatible = "maxim,max15301"; 348 reg = <0x18>; 349 }; 350 max15303@1a { /* u49 */ 351 compatible = "maxim,max15303"; 352 reg = <0x1a>; 353 }; 354 max15303@1d { /* u18 */ 355 compatible = "maxim,max15303"; 356 reg = <0x1d>; 357 }; 358 max15303@20 { /* u8 */ 359 compatible = "maxim,max15303"; 360 status = "disabled"; /* unreachable */ 361 reg = <0x20>; 362 }; 363 364 max20751@72 { /* u95 */ 365 compatible = "maxim,max20751"; 366 reg = <0x72>; 367 }; 368 max20751@73 { /* u96 */ 369 compatible = "maxim,max20751"; 370 reg = <0x73>; 371 }; 372 }; 373 /* Bus 3 is not connected */ 374 }; 375 }; 376 377 &i2c1 { 378 status = "okay"; 379 clock-frequency = <400000>; 380 381 /* PL i2c via PCA9306 - u45 */ 382 i2c-mux@74 { /* u34 */ 383 compatible = "nxp,pca9548"; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 reg = <0x74>; 387 i2c@0 { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <0>; 391 /* 392 * IIC_EEPROM 1kB memory which uses 256B blocks 393 * where every block has different address. 394 * 0 - 256B address 0x54 395 * 256B - 512B address 0x55 396 * 512B - 768B address 0x56 397 * 768B - 1024B address 0x57 398 */ 399 eeprom: eeprom@54 { /* u23 */ 400 compatible = "atmel,24c08"; 401 reg = <0x54>; 402 }; 403 }; 404 i2c@1 { 405 #address-cells = <1>; 406 #size-cells = <0>; 407 reg = <1>; 408 si5341: clock-generator@36 { /* SI5341 - u69 */ 409 compatible = "silabs,si5341"; 410 reg = <0x36>; 411 }; 412 413 }; 414 i2c@2 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 reg = <2>; 418 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 419 #clock-cells = <0>; 420 compatible = "silabs,si570"; 421 reg = <0x5d>; 422 temperature-stability = <50>; 423 factory-fout = <300000000>; 424 clock-frequency = <300000000>; 425 }; 426 }; 427 i2c@3 { 428 #address-cells = <1>; 429 #size-cells = <0>; 430 reg = <3>; 431 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 432 #clock-cells = <0>; 433 compatible = "silabs,si570"; 434 reg = <0x5d>; 435 temperature-stability = <50>; /* copy from zc702 */ 436 factory-fout = <156250000>; 437 clock-frequency = <148500000>; 438 }; 439 }; 440 i2c@4 { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 reg = <4>; 444 si5328: clock-generator@69 {/* SI5328 - u20 */ 445 compatible = "silabs,si5328"; 446 reg = <0x69>; 447 /* 448 * Chip has interrupt present connected to PL 449 * interrupt-parent = <&>; 450 * interrupts = <>; 451 */ 452 }; 453 }; 454 /* 5 - 7 unconnected */ 455 }; 456 457 i2c-mux@75 { 458 compatible = "nxp,pca9548"; /* u135 */ 459 #address-cells = <1>; 460 #size-cells = <0>; 461 reg = <0x75>; 462 463 i2c@0 { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 reg = <0>; 467 /* HPC0_IIC */ 468 }; 469 i2c@1 { 470 #address-cells = <1>; 471 #size-cells = <0>; 472 reg = <1>; 473 /* HPC1_IIC */ 474 }; 475 i2c@2 { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 reg = <2>; 479 /* SYSMON */ 480 }; 481 i2c@3 { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 reg = <3>; 485 /* DDR4 SODIMM */ 486 dev@19 { 487 reg = <0x19>; 488 }; 489 dev@30 { 490 reg = <0x30>; 491 }; 492 dev@35 { 493 reg = <0x35>; 494 }; 495 dev@36 { 496 reg = <0x36>; 497 }; 498 dev@51 { 499 reg = <0x51>; 500 }; 501 }; 502 i2c@4 { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 reg = <4>; 506 /* SEP 3 */ 507 }; 508 i2c@5 { 509 #address-cells = <1>; 510 #size-cells = <0>; 511 reg = <5>; 512 /* SEP 2 */ 513 }; 514 i2c@6 { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 reg = <6>; 518 /* SEP 1 */ 519 }; 520 i2c@7 { 521 #address-cells = <1>; 522 #size-cells = <0>; 523 reg = <7>; 524 /* SEP 0 */ 525 }; 526 }; 527 }; 528 529 &pcie { 530 status = "okay"; 531 }; 532 533 &qspi { 534 status = "okay"; 535 is-dual = <1>; 536 flash@0 { 537 compatible = "m25p80"; /* 32MB */ 538 #address-cells = <1>; 539 #size-cells = <1>; 540 reg = <0x0>; 541 spi-tx-bus-width = <1>; 542 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 543 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 544 partition@qspi-fsbl-uboot { /* for testing purpose */ 545 label = "qspi-fsbl-uboot"; 546 reg = <0x0 0x100000>; 547 }; 548 partition@qspi-linux { /* for testing purpose */ 549 label = "qspi-linux"; 550 reg = <0x100000 0x500000>; 551 }; 552 partition@qspi-device-tree { /* for testing purpose */ 553 label = "qspi-device-tree"; 554 reg = <0x600000 0x20000>; 555 }; 556 partition@qspi-rootfs { /* for testing purpose */ 557 label = "qspi-rootfs"; 558 reg = <0x620000 0x5E0000>; 559 }; 560 }; 561 }; 562 563 &rtc { 564 status = "okay"; 565 }; 566 567 &sata { 568 status = "okay"; 569 /* SATA OOB timing settings */ 570 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 571 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 572 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 573 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 574 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 575 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 576 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 577 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 578 phy-names = "sata-phy"; 579 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; 580 }; 581 582 /* SD1 with level shifter */ 583 &sdhci1 { 584 status = "okay"; 585 no-1-8-v; /* for 1.0 silicon */ 586 xlnx,mio_bank = <1>; 587 }; 588 589 &serdes { 590 status = "okay"; 591 }; 592 593 &uart0 { 594 status = "okay"; 595 }; 596 597 &uart1 { 598 status = "okay"; 599 }; 600 601 /* ULPI SMSC USB3320 */ 602 &usb0 { 603 status = "okay"; 604 }; 605 606 &dwc3_0 { 607 status = "okay"; 608 dr_mode = "host"; 609 snps,usb3_lpm_capable; 610 phy-names = "usb3-phy"; 611 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; 612 maximum-speed = "super-speed"; 613 }; 614 615 &watchdog0 { 616 status = "okay"; 617 }; 618 619 &xilinx_ams { 620 status = "okay"; 621 }; 622 623 &ams_ps { 624 status = "okay"; 625 }; 626 627 &ams_pl { 628 status = "okay"; 629 }; 630 631 &xilinx_drm { 632 status = "okay"; 633 clocks = <&si570_1>; 634 }; 635 636 &xlnx_dp { 637 status = "okay"; 638 }; 639 640 &xlnx_dp_sub { 641 status = "okay"; 642 xlnx,vid-clk-pl; 643 }; 644 645 &xlnx_dp_snd_pcm0 { 646 status = "okay"; 647 }; 648 649 &xlnx_dp_snd_pcm1 { 650 status = "okay"; 651 }; 652 653 &xlnx_dp_snd_card { 654 status = "okay"; 655 }; 656 657 &xlnx_dp_snd_codec0 { 658 status = "okay"; 659 }; 660 661 &xlnx_dpdma { 662 status = "okay"; 663 }; 664
