1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * hardware_am43xx.h 4 * 5 * AM43xx hardware specific header 6 * 7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 8 */ 9 10 #ifndef __AM43XX_HARDWARE_AM43XX_H 11 #define __AM43XX_HARDWARE_AM43XX_H 12 13 /* Module base addresses */ 14 15 /* L3 Fast Configuration Bandwidth Limiter Base Address */ 16 #define L3F_CFG_BWLIMITER 0x44005200 17 18 /* UART Base Address */ 19 #define UART0_BASE 0x44E09000 20 21 /* GPIO Base address */ 22 #define GPIO2_BASE 0x481AC000 23 24 /* Watchdog Timer */ 25 #define WDT_BASE 0x44E35000 26 27 /* Control Module Base Address */ 28 #define CTRL_BASE 0x44E10000 29 #define CTRL_DEVICE_BASE 0x44E10600 30 31 /* PRCM Base Address */ 32 #define PRCM_BASE 0x44DF0000 33 #define CM_WKUP 0x44DF2800 34 #define CM_PER 0x44DF8800 35 #define CM_DPLL 0x44DF4200 36 #define CM_RTC 0x44DF8500 37 38 #define PRM_RSTCTRL (PRCM_BASE + 0x4000) 39 #define PRM_RSTST (PRM_RSTCTRL + 4) 40 41 /* VTP Base address */ 42 #define VTP0_CTRL_ADDR 0x44E10E0C 43 #define VTP1_CTRL_ADDR 0x48140E10 44 45 /* USB CTRL Base Address */ 46 #define USB1_CTRL 0x44e10628 47 #define USB1_CTRL_CM_PWRDN BIT(0) 48 #define USB1_CTRL_OTG_PWRDN BIT(1) 49 50 /* DDR Base address */ 51 #define DDR_PHY_CMD_ADDR 0x44E12000 52 #define DDR_PHY_DATA_ADDR 0x44E120C8 53 #define DDR_PHY_CMD_ADDR2 0x47C0C800 54 #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 55 #define DDR_DATA_REGS_NR 2 56 57 /* CPSW Config space */ 58 #define CPSW_MDIO_BASE 0x4A101000 59 60 /* RTC base address */ 61 #define RTC_BASE 0x44E3E000 62 63 /* USB OTG */ 64 #define USB_OTG_SS1_BASE 0x48390000 65 #define USB_OTG_SS1_GLUE_BASE 0x48380000 66 #define USB2_PHY1_POWER 0x44E10620 67 68 #define USB_OTG_SS2_BASE 0x483D0000 69 #define USB_OTG_SS2_GLUE_BASE 0x483C0000 70 #define USB2_PHY2_POWER 0x44E10628 71 72 /* USB Clock Control */ 73 #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) 74 #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) 75 #define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) 76 #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) 77 78 #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) 79 #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) 80 #define USBPHYOCPSCP_MODULE_EN (1 << 1) 81 #define CM_DEVICE_INST 0x44df4100 82 #define PRM_DEVICE_INST 0x44df4000 83 84 #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) 85 #define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) 86 87 /* EDMA3 Base Address */ 88 #define EDMA3_BASE 0x49000000 89 90 #endif /* __AM43XX_HARDWARE_AM43XX_H */ 91
