1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * hardware_ti814x.h 4 * 5 * TI814x hardware specific header 6 * 7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 8 */ 9 10 #ifndef __AM33XX_HARDWARE_TI814X_H 11 #define __AM33XX_HARDWARE_TI814X_H 12 13 /* Module base addresses */ 14 15 /* UART Base Address */ 16 #define UART0_BASE 0x48020000 17 18 /* Watchdog Timer */ 19 #define WDT_BASE 0x481C7000 20 21 /* Control Module Base Address */ 22 #define CTRL_BASE 0x48140000 23 #define CTRL_DEVICE_BASE 0x48140600 24 25 /* PRCM Base Address */ 26 #define PRCM_BASE 0x48180000 27 #define CM_PER 0x44E00000 28 #define CM_WKUP 0x44E00400 29 30 #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) 31 #define PRM_RSTST (PRM_RSTCTRL + 8) 32 33 /* PLL Subsystem Base Address */ 34 #define PLL_SUBSYS_BASE 0x481C5000 35 36 /* VTP Base address */ 37 #define VTP0_CTRL_ADDR 0x48140E0C 38 #define VTP1_CTRL_ADDR 0x48140E10 39 40 /* DDR Base address */ 41 #define DDR_PHY_CMD_ADDR 0x47C0C400 42 #define DDR_PHY_DATA_ADDR 0x47C0C4C8 43 #define DDR_PHY_CMD_ADDR2 0x47C0C800 44 #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 45 #define DDR_DATA_REGS_NR 4 46 47 #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) 48 #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE 49 50 /* CPSW Config space */ 51 #define CPSW_MDIO_BASE 0x4A100800 52 53 /* RTC base address */ 54 #define RTC_BASE 0x480C0000 55 56 /* OTG */ 57 #define USB0_OTG_BASE 0x47401000 58 #define USB1_OTG_BASE 0x47401800 59 60 #endif /* __AM33XX_HARDWARE_TI814X_H */ 61
