1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2011 4 * eInfochips Ltd. <www.einfochips.com> 5 * Written-by: Ajay Bhargav <contact (at) 8051projects.net> 6 * 7 * (C) Copyright 2010 8 * Marvell Semiconductor <www.marvell.com> 9 */ 10 11 #ifndef __ARMADA100_SPI_H_ 12 #define __ARMADA100_SPI_H_ 13 14 #include <asm/arch/armada100.h> 15 16 #define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE 17 #define SSP_REG_BASE(x) CAT_BASE_ADDR(x) 18 19 /* 20 * SSP Serial Port Registers 21 * refer Appendix A.26 22 */ 23 struct ssp_reg { 24 u32 sscr0; /* SSP Control Register 0 - 0x000 */ 25 u32 sscr1; /* SSP Control Register 1 - 0x004 */ 26 u32 sssr; /* SSP Status Register - 0x008 */ 27 u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ 28 u32 ssdr; /* SSP Data Register - 0x010 */ 29 u32 pad1[5]; 30 u32 ssto; /* SSP Timeout Register - 0x028 */ 31 u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ 32 u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ 33 u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ 34 u32 sstss; /* SSP Timeslot Status Register - 0x038 */ 35 }; 36 37 #define DEFAULT_WORD_LEN 8 38 #define SSP_FLUSH_NUM 0x2000 39 #define RX_THRESH_DEF 8 40 #define TX_THRESH_DEF 8 41 #define TIMEOUT_DEF 1000 42 43 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ 44 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ 45 #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ 46 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity 47 setting */ 48 #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ 49 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ 50 #define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ 51 #define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ 52 53 #define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ 54 #define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ 55 #define SSCR1_TINTE (1 << 19) /* Receiver Time-out 56 Interrupt enable */ 57 58 #define SSCR0_DSS 0x0f /* Data Size Select (mask) */ 59 #define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ 60 #define SSCR0_FRF 0x30 /* FRame Format (mask) */ 61 #define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial 62 Peripheral Interface */ 63 #define SSCR0_TI (0x1 << 4) /* TI's Synchronous 64 Serial Protocol (SSP) */ 65 #define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ 66 #define SSCR0_ECS (1 << 6) /* External clock select */ 67 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port 68 Enable */ 69 70 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ 71 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ 72 #define SSSR_BSY (1 << 4) /* SSP Busy */ 73 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ 74 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ 75 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ 76 #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ 77 78 #endif /* __ARMADA100_SPI_H_ */ 79
