1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __MX7D_RDC_H__ 7 #define __MX7D_RDC_H__ 8 9 #define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */ 10 11 enum { 12 RDC_PER_GPIO1 = 0, 13 RDC_PER_GPIO2, 14 RDC_PER_GPIO3, 15 RDC_PER_GPIO4, 16 RDC_PER_GPIO5, 17 RDC_PER_GPIO6, 18 RDC_PER_GPIO7, 19 RDC_PER_IOMUXC_LPSR_GPR, 20 RDC_PER_WDOG1, 21 RDC_PER_WDOG2, 22 RDC_PER_WDOG3, 23 RDC_PER_WDOG4, 24 RDC_PER_IOMUXC_LPSR, 25 RDC_PER_GPT1, 26 RDC_PER_GPT2, 27 RDC_PER_GPT3, 28 RDC_PER_GPT4, 29 RDC_PER_ROMCP, 30 RDC_PER_KPP, 31 RDC_PER_IOMUXC, 32 RDC_PER_IOMUXCGPR, 33 RDC_PER_OCOTP, 34 RDC_PER_ANATOP_DIG, 35 RDC_PER_SNVS_HP, 36 RDC_PER_CCM, 37 RDC_PER_SRC, 38 RDC_PER_GPC, 39 RDC_PER_SEMA1, 40 RDC_PER_SEMA2, 41 RDC_PER_RDC, 42 RDC_PER_CSU, 43 RDC_PER_RESERVED1, 44 RDC_PER_RESERVED2, 45 RDC_PER_ADC1, 46 RDC_PER_ADC2, 47 RDC_PER_ECSPI4, 48 RDC_PER_FLEX_TIMER1, 49 RDC_PER_FLEX_TIMER2, 50 RDC_PER_PWM1, 51 RDC_PER_PWM2, 52 RDC_PER_PWM3, 53 RDC_PER_PWM4, 54 RDC_PER_SYSTEM_COUNTER_READ, 55 RDC_PER_SYSTEM_COUNTER_COMPARE, 56 RDC_PER_SYSTEM_COUNTER_CONTROL, 57 RDC_PER_PCIE_PHY, 58 RDC_PER_RESERVED3, 59 RDC_PER_EPDC, 60 RDC_PER_PXP, 61 RDC_PER_CSI, 62 RDC_PER_RESERVED4, 63 RDC_PER_LCDIF, 64 RDC_PER_RESERVED5, 65 RDC_PER_MIPI_CSI, 66 RDC_PER_MIPI_DSI, 67 RDC_PER_RESERVED6, 68 RDC_PER_TZASC, 69 RDC_PER_DDR_PHY, 70 RDC_PER_DDRC, 71 RDC_PER_RESERVED7, 72 RDC_PER_PERFMON1, 73 RDC_PER_PERFMON2, 74 RDC_PER_AXI_DEBUG_MON, 75 RDC_PER_QOSC, 76 RDC_PER_FLEXCAN1, 77 RDC_PER_FLEXCAN2, 78 RDC_PER_I2C1, 79 RDC_PER_I2C2, 80 RDC_PER_I2C3, 81 RDC_PER_I2C4, 82 RDC_PER_UART4, 83 RDC_PER_UART5, 84 RDC_PER_UART6, 85 RDC_PER_UART7, 86 RDC_PER_MU_A, 87 RDC_PER_MU_B, 88 RDC_PER_SEMAPHORE_HS, 89 RDC_PER_USB_PL301, 90 RDC_PER_RESERVED8, 91 RDC_PER_RESERVED9, 92 RDC_PER_RESERVED10, 93 RDC_PER_USB1, 94 RDC_PER_USB2, 95 RDC_PER_USB3, 96 RDC_PER_USDHC1, 97 RDC_PER_USDHC2, 98 RDC_PER_USDHC3, 99 RDC_PER_RESERVED11, 100 RDC_PER_RESERVED12, 101 RDC_PER_SIM1, 102 RDC_PER_SIM2, 103 RDC_PER_QSPI, 104 RDC_PER_WEIM, 105 RDC_PER_SDMA, 106 RDC_PER_ENET1, 107 RDC_PER_ENET2, 108 RDC_PER_RESERVED13, 109 RDC_PER_RESERVED14, 110 RDC_PER_ECSPI1, 111 RDC_PER_ECSPI2, 112 RDC_PER_ECSPI3, 113 RDC_PER_RESERVED15, 114 RDC_PER_UART1, 115 RDC_PER_UART2, 116 RDC_PER_UART3, 117 RDC_PER_RESERVED16, 118 RDC_PER_SAI1, 119 RDC_PER_SAI2, 120 RDC_PER_SAI3, 121 RDC_PER_RESERVED17, 122 RDC_PER_RESERVED18, 123 RDC_PER_SPBA, 124 RDC_PER_DAP, 125 RDC_PER_RESERVED19, 126 RDC_PER_RESERVED20, 127 RDC_PER_RESERVED21, 128 RDC_PER_CAAM, 129 RDC_PER_RESERVED22, 130 }; 131 132 enum { 133 RDC_MA_A7 = 0, 134 RDC_MA_M4, 135 RDC_MA_PCIE, 136 RDC_MA_CSI, 137 RDC_MA_EPDC, 138 RDC_MA_LCDIF, 139 RDC_MA_DISPLAY_PORT, 140 RDC_MA_PXP, 141 RDC_MA_CORESIGHT, 142 RDC_MA_DAP, 143 RDC_MA_CAAM, 144 RDC_MA_SDMA_PERI, 145 RDC_MA_SDMA_BURST, 146 RDC_MA_APBHDMA, 147 RDC_MA_RAWNAND, 148 RDC_MA_USDHC1, 149 RDC_MA_USDHC2, 150 RDC_MA_USDHC3, 151 RDC_MA_NC1, 152 RDC_MA_USB, 153 RDC_MA_NC2, 154 RDC_MA_TEST, 155 RDC_MA_ENET1_TX, 156 RDC_MA_ENET1_RX, 157 RDC_MA_ENET2_TX, 158 RDC_MA_ENET2_RX, 159 RDC_MA_SDMA, 160 }; 161 162 #endif /* __MX7D_RDC_H__*/ 163
