1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Freescale i.MX28 I2C Register Definitions 4 * 5 * Copyright (C) 2011 Marek Vasut <marek.vasut (at) gmail.com> 6 * on behalf of DENX Software Engineering GmbH 7 */ 8 9 #ifndef __MX28_REGS_I2C_H__ 10 #define __MX28_REGS_I2C_H__ 11 12 #include <asm/mach-imx/regs-common.h> 13 14 #ifndef __ASSEMBLY__ 15 struct mxs_i2c_regs { 16 mxs_reg_32(hw_i2c_ctrl0) 17 mxs_reg_32(hw_i2c_timing0) 18 mxs_reg_32(hw_i2c_timing1) 19 mxs_reg_32(hw_i2c_timing2) 20 mxs_reg_32(hw_i2c_ctrl1) 21 mxs_reg_32(hw_i2c_stat) 22 mxs_reg_32(hw_i2c_queuectrl) 23 mxs_reg_32(hw_i2c_queuestat) 24 mxs_reg_32(hw_i2c_queuecmd) 25 mxs_reg_32(hw_i2c_queuedata) 26 mxs_reg_32(hw_i2c_data) 27 mxs_reg_32(hw_i2c_debug0) 28 mxs_reg_32(hw_i2c_debug1) 29 mxs_reg_32(hw_i2c_version) 30 }; 31 #endif 32 33 #define I2C_CTRL_SFTRST (1 << 31) 34 #define I2C_CTRL_CLKGATE (1 << 30) 35 #define I2C_CTRL_RUN (1 << 29) 36 #define I2C_CTRL_PREACK (1 << 27) 37 #define I2C_CTRL_ACKNOWLEDGE (1 << 26) 38 #define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25) 39 #define I2C_CTRL_MULTI_MASTER (1 << 23) 40 #define I2C_CTRL_CLOCK_HELD (1 << 22) 41 #define I2C_CTRL_RETAIN_CLOCK (1 << 21) 42 #define I2C_CTRL_POST_SEND_STOP (1 << 20) 43 #define I2C_CTRL_PRE_SEND_START (1 << 19) 44 #define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18) 45 #define I2C_CTRL_MASTER_MODE (1 << 17) 46 #define I2C_CTRL_DIRECTION (1 << 16) 47 #define I2C_CTRL_XFER_COUNT_MASK 0xffff 48 #define I2C_CTRL_XFER_COUNT_OFFSET 0 49 50 #define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16) 51 #define I2C_TIMING0_HIGH_COUNT_OFFSET 16 52 #define I2C_TIMING0_RCV_COUNT_MASK 0x3ff 53 #define I2C_TIMING0_RCV_COUNT_OFFSET 0 54 55 #define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16) 56 #define I2C_TIMING1_LOW_COUNT_OFFSET 16 57 #define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff 58 #define I2C_TIMING1_XMIT_COUNT_OFFSET 0 59 60 #define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16) 61 #define I2C_TIMING2_BUS_FREE_OFFSET 16 62 #define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff 63 #define I2C_TIMING2_LEADIN_COUNT_OFFSET 0 64 65 #define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30) 66 #define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29) 67 #define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28) 68 #define I2C_CTRL1_ACK_MODE (1 << 27) 69 #define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26) 70 #define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25) 71 #define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24) 72 #define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16) 73 #define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16 74 #define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15) 75 #define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14) 76 #define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13) 77 #define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) 78 #define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11) 79 #define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10) 80 #define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9) 81 #define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8) 82 #define I2C_CTRL1_BUS_FREE_IRQ (1 << 7) 83 #define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6) 84 #define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5) 85 #define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4) 86 #define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3) 87 #define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2) 88 #define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1) 89 #define I2C_CTRL1_SLAVE_IRQ (1 << 0) 90 91 #define I2C_STAT_MASTER_PRESENT (1 << 31) 92 #define I2C_STAT_SLAVE_PRESENT (1 << 30) 93 #define I2C_STAT_ANY_ENABLED_IRQ (1 << 29) 94 #define I2C_STAT_GOT_A_NAK (1 << 28) 95 #define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16) 96 #define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16 97 #define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15) 98 #define I2C_STAT_SLAVE_FOUND (1 << 14) 99 #define I2C_STAT_SLAVE_SEARCHING (1 << 13) 100 #define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12) 101 #define I2C_STAT_BUS_BUSY (1 << 11) 102 #define I2C_STAT_CLK_GEN_BUSY (1 << 10) 103 #define I2C_STAT_DATA_ENGINE_BUSY (1 << 9) 104 #define I2C_STAT_SLAVE_BUSY (1 << 8) 105 #define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7) 106 #define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6) 107 #define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) 108 #define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) 109 #define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3) 110 #define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2) 111 #define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1) 112 #define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0) 113 114 #define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16) 115 #define I2C_QUEUECTRL_RD_THRESH_OFFSET 16 116 #define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8) 117 #define I2C_QUEUECTRL_WR_THRESH_OFFSET 8 118 #define I2C_QUEUECTRL_QUEUE_RUN (1 << 5) 119 #define I2C_QUEUECTRL_RD_CLEAR (1 << 4) 120 #define I2C_QUEUECTRL_WR_CLEAR (1 << 3) 121 #define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2) 122 #define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1) 123 #define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0) 124 125 #define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14) 126 #define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13) 127 #define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8) 128 #define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8 129 #define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6) 130 #define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5) 131 #define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f 132 #define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0 133 134 #define I2C_QUEUECMD_PREACK (1 << 27) 135 #define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26) 136 #define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25) 137 #define I2C_QUEUECMD_MULTI_MASTER (1 << 23) 138 #define I2C_QUEUECMD_CLOCK_HELD (1 << 22) 139 #define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21) 140 #define I2C_QUEUECMD_POST_SEND_STOP (1 << 20) 141 #define I2C_QUEUECMD_PRE_SEND_START (1 << 19) 142 #define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18) 143 #define I2C_QUEUECMD_MASTER_MODE (1 << 17) 144 #define I2C_QUEUECMD_DIRECTION (1 << 16) 145 #define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff 146 #define I2C_QUEUECMD_XFER_COUNT_OFFSET 0 147 148 #define I2C_QUEUEDATA_DATA_MASK 0xffffffff 149 #define I2C_QUEUEDATA_DATA_OFFSET 0 150 151 #define I2C_DATA_DATA_MASK 0xffffffff 152 #define I2C_DATA_DATA_OFFSET 0 153 154 #define I2C_DEBUG0_DMAREQ (1 << 31) 155 #define I2C_DEBUG0_DMAENDCMD (1 << 30) 156 #define I2C_DEBUG0_DMAKICK (1 << 29) 157 #define I2C_DEBUG0_DMATERMINATE (1 << 28) 158 #define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26) 159 #define I2C_DEBUG0_STATE_VALUE_OFFSET 26 160 #define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16) 161 #define I2C_DEBUG0_DMA_STATE_OFFSET 16 162 #define I2C_DEBUG0_START_TOGGLE (1 << 15) 163 #define I2C_DEBUG0_STOP_TOGGLE (1 << 14) 164 #define I2C_DEBUG0_GRAB_TOGGLE (1 << 13) 165 #define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12) 166 #define I2C_DEBUG0_STATE_LATCH (1 << 11) 167 #define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10) 168 #define I2C_DEBUG0_STATE_STATE_MASK 0x3ff 169 #define I2C_DEBUG0_STATE_STATE_OFFSET 0 170 171 #define I2C_DEBUG1_I2C_CLK_IN (1 << 31) 172 #define I2C_DEBUG1_I2C_DATA_IN (1 << 30) 173 #define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24) 174 #define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24 175 #define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16) 176 #define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16 177 #define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9) 178 #define I2C_DEBUG1_LST_MODE_OFFSET 9 179 #define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8) 180 #define I2C_DEBUG1_FORCE_CLK_ON (1 << 4) 181 #define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3) 182 #define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2) 183 #define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1) 184 #define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0) 185 186 #define I2C_VERSION_MAJOR_MASK (0xff << 24) 187 #define I2C_VERSION_MAJOR_OFFSET 24 188 #define I2C_VERSION_MINOR_MASK (0xff << 16) 189 #define I2C_VERSION_MINOR_OFFSET 16 190 #define I2C_VERSION_STEP_MASK 0xffff 191 #define I2C_VERSION_STEP_OFFSET 0 192 193 #endif /* __MX28_REGS_I2C_H__ */ 194
