1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * NVIDIA Tegra I2C controller 4 * 5 * Copyright 2010-2011 NVIDIA Corporation 6 */ 7 8 #ifndef _TEGRA_I2C_H_ 9 #define _TEGRA_I2C_H_ 10 11 #include <asm/types.h> 12 13 enum { 14 I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */ 15 I2C_FIFO_DEPTH = 8, /* I2C fifo depth */ 16 }; 17 18 enum i2c_transaction_flags { 19 I2C_IS_WRITE = 0x1, /* for I2C write operation */ 20 I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ 21 I2C_USE_REPEATED_START = 0x4, /* for repeat start */ 22 I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ 23 I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ 24 I2C_NO_STOP = 0x20, 25 }; 26 27 /* Contians the I2C transaction details */ 28 struct i2c_trans_info { 29 /* flags to indicate the transaction details */ 30 enum i2c_transaction_flags flags; 31 u32 address; /* I2C slave device address */ 32 u32 num_bytes; /* number of bytes to be transferred */ 33 /* 34 * Send/receive buffer. For the I2C send operation this buffer should 35 * be filled with the data to be sent to the slave device. For the I2C 36 * receive operation this buffer is filled with the data received from 37 * the slave device. 38 */ 39 u8 *buf; 40 int is_10bit_address; 41 }; 42 43 struct i2c_control { 44 u32 tx_fifo; 45 u32 rx_fifo; 46 u32 packet_status; 47 u32 fifo_control; 48 u32 fifo_status; 49 u32 int_mask; 50 u32 int_status; 51 }; 52 53 struct dvc_ctlr { 54 u32 ctrl1; /* 00: DVC_CTRL_REG1 */ 55 u32 ctrl2; /* 04: DVC_CTRL_REG2 */ 56 u32 ctrl3; /* 08: DVC_CTRL_REG3 */ 57 u32 status; /* 0C: DVC_STATUS_REG */ 58 u32 ctrl; /* 10: DVC_I2C_CTRL_REG */ 59 u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */ 60 u32 reserved_0[2]; /* 18: */ 61 u32 req; /* 20: DVC_REQ_REGISTER */ 62 u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */ 63 u32 reserved_1[6]; /* 28: */ 64 u32 cnfg; /* 40: DVC_I2C_CNFG */ 65 u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */ 66 u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */ 67 u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */ 68 u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */ 69 u32 reserved_2[2]; /* 54: */ 70 u32 i2c_status; /* 5C: DVC_I2C_STATUS */ 71 struct i2c_control control; /* 60 ~ 78 */ 72 }; 73 74 struct i2c_ctlr { 75 u32 cnfg; /* 00: I2C_I2C_CNFG */ 76 u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */ 77 u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */ 78 u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */ 79 u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */ 80 u32 reserved_0[2]; /* 14: */ 81 u32 status; /* 1C: I2C_I2C_STATUS */ 82 u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */ 83 u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */ 84 u32 sl_status; /* 28: I2C_I2C_SL_STATUS */ 85 u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */ 86 u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */ 87 u32 reserved_1[2]; /* 34: */ 88 u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ 89 u32 reserved_2[4]; /* 40: */ 90 struct i2c_control control; /* 50 ~ 68 */ 91 u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */ 92 }; 93 94 /* bit fields definitions for IO Packet Header 1 format */ 95 #define PKT_HDR1_PROTOCOL_SHIFT 4 96 #define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT) 97 #define PKT_HDR1_CTLR_ID_SHIFT 12 98 #define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT) 99 #define PKT_HDR1_PKT_ID_SHIFT 16 100 #define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT) 101 #define PROTOCOL_TYPE_I2C 1 102 103 /* bit fields definitions for IO Packet Header 2 format */ 104 #define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0 105 #define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT) 106 107 /* bit fields definitions for IO Packet Header 3 format */ 108 #define PKT_HDR3_READ_MODE_SHIFT 19 109 #define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) 110 #define PKT_HDR3_REPEAT_START_SHIFT 16 111 #define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT) 112 #define PKT_HDR3_SLAVE_ADDR_SHIFT 0 113 #define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) 114 115 #define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26 116 #define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \ 117 (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT) 118 119 /* I2C_CNFG */ 120 #define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11 121 #define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT) 122 #define I2C_CNFG_PACKET_MODE_SHIFT 10 123 #define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT) 124 125 /* I2C_SL_CNFG */ 126 #define I2C_SL_CNFG_NEWSL_SHIFT 2 127 #define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT) 128 129 /* I2C_FIFO_STATUS */ 130 #define TX_FIFO_FULL_CNT_SHIFT 0 131 #define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT) 132 #define TX_FIFO_EMPTY_CNT_SHIFT 4 133 #define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT) 134 135 /* I2C_INTERRUPT_STATUS */ 136 #define I2C_INT_XFER_COMPLETE_SHIFT 7 137 #define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT) 138 #define I2C_INT_NO_ACK_SHIFT 3 139 #define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT) 140 #define I2C_INT_ARBITRATION_LOST_SHIFT 2 141 #define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) 142 143 /* I2C_CLK_DIVISOR_REGISTER */ 144 #define CLK_DIV_STD_FAST_MODE 0x19 145 #define CLK_DIV_HS_MODE 1 146 #define CLK_MULT_STD_FAST_MODE 8 147 148 /** 149 * Returns the bus number of the DVC controller 150 * 151 * @return number of bus, or -1 if there is no DVC active 152 */ 153 int tegra_i2c_get_dvc_bus(struct udevice **busp); 154 155 #endif /* _TEGRA_I2C_H_ */ 156
