1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Texas Instruments Keystone SerDes driver 4 * 5 * (C) Copyright 2014 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 9 #ifndef __TI_KEYSTONE_SERDES_H__ 10 #define __TI_KEYSTONE_SERDES_H__ 11 12 /* SERDES Reference clock */ 13 enum ks2_serdes_clock { 14 SERDES_CLOCK_100M, /* 100 MHz */ 15 SERDES_CLOCK_122P88M, /* 122.88 MHz */ 16 SERDES_CLOCK_125M, /* 125 MHz */ 17 SERDES_CLOCK_156P25M, /* 156.25 MHz */ 18 SERDES_CLOCK_312P5M, /* 312.5 MHz */ 19 }; 20 21 /* SERDES Lane Baud Rate */ 22 enum ks2_serdes_rate { 23 SERDES_RATE_4P9152G, /* 4.9152 GBaud */ 24 SERDES_RATE_5G, /* 5 GBaud */ 25 SERDES_RATE_6P144G, /* 6.144 GBaud */ 26 SERDES_RATE_6P25G, /* 6.25 GBaud */ 27 SERDES_RATE_10p3125g, /* 10.3215 GBaud */ 28 SERDES_RATE_12p5g, /* 12.5 GBaud */ 29 }; 30 31 /* SERDES Lane Rate Mode */ 32 enum ks2_serdes_rate_mode { 33 SERDES_FULL_RATE, 34 SERDES_HALF_RATE, 35 SERDES_QUARTER_RATE, 36 }; 37 38 /* SERDES PHY TYPE */ 39 enum ks2_serdes_interface { 40 SERDES_PHY_SGMII, 41 SERDES_PHY_PCSR, /* XGE SERDES */ 42 }; 43 44 struct ks2_serdes { 45 enum ks2_serdes_clock clk; 46 enum ks2_serdes_rate rate; 47 enum ks2_serdes_rate_mode rate_mode; 48 enum ks2_serdes_interface intf; 49 u32 loopback; 50 }; 51 52 int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes); 53 54 #endif /* __TI_KEYSTONE_SERDES_H__ */ 55
