1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SoC-specific code for tms320dm644x chips 4 * 5 * Copyright (C) 2007 Sergey Kubushyn <ksi (at) koi8.net> 6 * Copyright (C) 2008 Lyrtech <www.lyrtech.com> 7 * Copyright (C) 2004 Texas Instruments. 8 */ 9 10 #include <common.h> 11 #include <asm/arch/hardware.h> 12 13 14 #define PINMUX0_EMACEN (1 << 31) 15 #define PINMUX0_AECS5 (1 << 11) 16 #define PINMUX0_AECS4 (1 << 10) 17 18 #define PINMUX1_I2C (1 << 7) 19 #define PINMUX1_UART1 (1 << 1) 20 #define PINMUX1_UART0 (1 << 0) 21 22 23 void davinci_enable_uart0(void) 24 { 25 lpsc_on(DAVINCI_LPSC_UART0); 26 27 /* Bringup UART0 out of reset */ 28 REG(UART0_PWREMU_MGMT) = 0x00006001; 29 30 /* Enable UART0 MUX lines */ 31 REG(PINMUX1) |= PINMUX1_UART0; 32 } 33 34 #ifdef CONFIG_DRIVER_TI_EMAC 35 void davinci_enable_emac(void) 36 { 37 lpsc_on(DAVINCI_LPSC_EMAC); 38 lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); 39 lpsc_on(DAVINCI_LPSC_MDIO); 40 41 /* Enable GIO3.3V cells used for EMAC */ 42 REG(VDD3P3V_PWDN) = 0; 43 44 /* Enable EMAC. */ 45 REG(PINMUX0) |= PINMUX0_EMACEN; 46 } 47 #endif 48 49 #ifdef CONFIG_SYS_I2C_DAVINCI 50 void davinci_enable_i2c(void) 51 { 52 lpsc_on(DAVINCI_LPSC_I2C); 53 54 /* Enable I2C pin Mux */ 55 REG(PINMUX1) |= PINMUX1_I2C; 56 } 57 #endif 58 59 void davinci_errata_workarounds(void) 60 { 61 /* 62 * Workaround for TMS320DM6446 errata 1.3.22: 63 * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset 64 * Revision(s) Affected: 1.3 and earlier 65 */ 66 REG(PSC_SILVER_BULLET) = 0; 67 68 /* 69 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) 70 * as suggested in TMS320DM6446 errata 2.1.2: 71 * 72 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions 73 * low priority modules can occupy the bus and prevent high priority 74 * modules like the VPSS from getting the required DDR2 throughput. 75 * A hex value of 0x20 should provide a good ARM (cache enabled) 76 * performance and still allow good utilization by the VPSS or other 77 * modules. 78 */ 79 REG(VBPR) = 0x20; 80 } 81
