1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018 Armadeus Systems 4 */ 5 6 #include <asm/arch/clock.h> 7 #include <asm/arch/crm_regs.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/iomux.h> 10 #include <asm/arch/mx6-pins.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/gpio.h> 13 #include <asm/mach-imx/iomux-v3.h> 14 #include <asm/io.h> 15 #include <common.h> 16 #include <environment.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #ifdef CONFIG_FEC_MXC 21 #include <miiphy.h> 22 23 #define MDIO_PAD_CTRL ( \ 24 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 25 PAD_CTL_DSE_40ohm \ 26 ) 27 28 #define ENET_PAD_CTRL_PU ( \ 29 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 30 PAD_CTL_DSE_40ohm \ 31 ) 32 33 #define ENET_PAD_CTRL_PD ( \ 34 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 35 PAD_CTL_DSE_40ohm \ 36 ) 37 38 #define ENET_CLK_PAD_CTRL ( \ 39 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ 40 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \ 41 ) 42 43 static iomux_v3_cfg_t const fec1_pads[] = { 44 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 45 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), 46 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 47 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 48 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 49 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 50 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), 51 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), 52 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), 53 /* PHY Int */ 54 MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), 55 /* PHY Reset */ 56 MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 57 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 58 }; 59 60 int board_phy_config(struct phy_device *phydev) 61 { 62 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); 63 64 if (phydev->drv->config) 65 phydev->drv->config(phydev); 66 67 return 0; 68 } 69 70 int board_eth_init(bd_t *bis) 71 { 72 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 73 struct gpio_desc rst; 74 int ret; 75 76 /* Use 50M anatop loopback REF_CLK1 for ENET1, 77 * clear gpr1[13], set gpr1[17] */ 78 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 79 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); 80 81 ret = enable_fec_anatop_clock(0, ENET_50MHZ); 82 if (ret) 83 return ret; 84 85 enable_enet_clk(1); 86 87 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 88 89 ret = dm_gpio_lookup_name("GPIO4_2", &rst); 90 if (ret) { 91 printf("Cannot get GPIO4_2\n"); 92 return ret; 93 } 94 95 ret = dm_gpio_request(&rst, "phy-rst"); 96 if (ret) { 97 printf("Cannot request GPIO4_2\n"); 98 return ret; 99 } 100 101 dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT); 102 dm_gpio_set_value(&rst, 0); 103 udelay(1000); 104 dm_gpio_set_value(&rst, 1); 105 106 return fecmxc_initialize(bis); 107 } 108 #endif /* CONFIG_FEC_MXC */ 109 110 int board_init(void) 111 { 112 /* Address of boot parameters */ 113 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 114 115 return 0; 116 } 117 118 int __weak opos6ul_board_late_init(void) 119 { 120 return 0; 121 } 122 123 int board_late_init(void) 124 { 125 struct src *psrc = (struct src *)SRC_BASE_ADDR; 126 unsigned reg = readl(&psrc->sbmr2); 127 128 /* In bootstrap don't use the env vars */ 129 if (((reg & 0x3000000) >> 24) == 0x1) { 130 set_default_env(NULL); 131 env_set("preboot", ""); 132 } 133 134 return opos6ul_board_late_init(); 135 } 136 137 int dram_init(void) 138 { 139 gd->ram_size = imx_ddr_size(); 140 141 return 0; 142 } 143 144 #ifdef CONFIG_SPL_BUILD 145 #include <asm/arch/mx6-ddr.h> 146 #include <linux/libfdt.h> 147 #include <spl.h> 148 149 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 150 .grp_addds = 0x00000030, 151 .grp_ddrmode_ctl = 0x00020000, 152 .grp_b0ds = 0x00000030, 153 .grp_ctlds = 0x00000030, 154 .grp_b1ds = 0x00000030, 155 .grp_ddrpke = 0x00000000, 156 .grp_ddrmode = 0x00020000, 157 .grp_ddr_type = 0x000c0000, 158 }; 159 160 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 161 .dram_dqm0 = 0x00000030, 162 .dram_dqm1 = 0x00000030, 163 .dram_ras = 0x00000030, 164 .dram_cas = 0x00000030, 165 .dram_odt0 = 0x00000030, 166 .dram_odt1 = 0x00000030, 167 .dram_sdba2 = 0x00000000, 168 .dram_sdclk_0 = 0x00000008, 169 .dram_sdqs0 = 0x00000038, 170 .dram_sdqs1 = 0x00000030, 171 .dram_reset = 0x00000030, 172 }; 173 174 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 175 .p0_mpwldectrl0 = 0x00070007, 176 .p0_mpdgctrl0 = 0x41490145, 177 .p0_mprddlctl = 0x40404546, 178 .p0_mpwrdlctl = 0x4040524D, 179 }; 180 181 struct mx6_ddr_sysinfo ddr_sysinfo = { 182 .dsize = 0, 183 .cs_density = 20, 184 .ncs = 1, 185 .cs1_mirror = 0, 186 .rtt_wr = 2, 187 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 188 .walat = 1, /* Write additional latency */ 189 .ralat = 5, /* Read additional latency */ 190 .mif3_mode = 3, /* Command prediction working mode */ 191 .bi_on = 1, /* Bank interleaving enabled */ 192 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 193 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 194 .ddr_type = DDR_TYPE_DDR3, 195 }; 196 197 static struct mx6_ddr3_cfg mem_ddr = { 198 .mem_speed = 800, 199 .density = 2, 200 .width = 16, 201 .banks = 8, 202 .rowaddr = 14, 203 .coladdr = 10, 204 .pagesz = 2, 205 .trcd = 1500, 206 .trcmin = 5250, 207 .trasmin = 3750, 208 }; 209 210 void board_boot_order(u32 *spl_boot_list) 211 { 212 unsigned int bmode = readl(&src_base->sbmr2); 213 214 if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */ 215 spl_boot_list[0] = BOOT_DEVICE_UART; 216 else 217 spl_boot_list[0] = spl_boot_device(); 218 } 219 220 static void ccgr_init(void) 221 { 222 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 223 224 writel(0xFFFFFFFF, &ccm->CCGR0); 225 writel(0xFFFFFFFF, &ccm->CCGR1); 226 writel(0xFFFFFFFF, &ccm->CCGR2); 227 writel(0xFFFFFFFF, &ccm->CCGR3); 228 writel(0xFFFFFFFF, &ccm->CCGR4); 229 writel(0xFFFFFFFF, &ccm->CCGR5); 230 writel(0xFFFFFFFF, &ccm->CCGR6); 231 writel(0xFFFFFFFF, &ccm->CCGR7); 232 } 233 234 static void spl_dram_init(void) 235 { 236 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 237 struct fuse_bank *bank = &ocotp->bank[4]; 238 struct fuse_bank4_regs *fuse = 239 (struct fuse_bank4_regs *)bank->fuse_regs; 240 int reg = readl(&fuse->gp1); 241 242 /* 512MB of RAM */ 243 if (reg & 0x1) { 244 mem_ddr.density = 4; 245 mem_ddr.rowaddr = 15; 246 mem_ddr.trcd = 1375; 247 mem_ddr.trcmin = 4875; 248 mem_ddr.trasmin = 3500; 249 } 250 251 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 252 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 253 } 254 255 void spl_board_init(void) 256 { 257 preloader_console_init(); 258 } 259 260 void board_init_f(ulong dummy) 261 { 262 ccgr_init(); 263 264 /* setup AIPS and disable watchdog */ 265 arch_cpu_init(); 266 267 /* setup GP timer */ 268 timer_init(); 269 270 /* DDR initialization */ 271 spl_dram_init(); 272 } 273 #endif /* CONFIG_SPL_BUILD */ 274
