1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * K2E: SoC definitions 4 * 5 * (C) Copyright 2012-2014 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 9 #ifndef __ASM_ARCH_HARDWARE_K2E_H 10 #define __ASM_ARCH_HARDWARE_K2E_H 11 12 /* PA SS Registers */ 13 #define KS2_PASS_BASE 0x24000000 14 15 /* Power and Sleep Controller (PSC) Domains */ 16 #define KS2_LPSC_MOD_RST 0 17 #define KS2_LPSC_USB_1 1 18 #define KS2_LPSC_USB 2 19 #define KS2_LPSC_EMIF25_SPI 3 20 #define KS2_LPSC_TSIP 4 21 #define KS2_LPSC_DEBUGSS_TRC 5 22 #define KS2_LPSC_TETB_TRC 6 23 #define KS2_LPSC_PKTPROC 7 24 #define KS2_LPSC_PA KS2_LPSC_PKTPROC 25 #define KS2_LPSC_SGMII 8 26 #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII 27 #define KS2_LPSC_CRYPTO 9 28 #define KS2_LPSC_PCIE 10 29 #define KS2_LPSC_VUSR0 12 30 #define KS2_LPSC_CHIP_SRSS 13 31 #define KS2_LPSC_MSMC 14 32 #define KS2_LPSC_EMIF4F_DDR3 23 33 #define KS2_LPSC_PCIE_1 27 34 #define KS2_LPSC_XGE 50 35 36 /* Chip Interrupt Controller */ 37 #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ 38 #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ 39 40 /* SGMII SerDes */ 41 #define KS2_SGMII_SERDES2_BASE 0x02324000 42 #define KS2_LANES_PER_SGMII_SERDES 4 43 44 /* Number of DSP cores */ 45 #define KS2_NUM_DSPS 1 46 47 /* NETCP pktdma */ 48 #define KS2_NETCP_PDMA_CTRL_BASE 0x24186000 49 #define KS2_NETCP_PDMA_TX_BASE 0x24187000 50 #define KS2_NETCP_PDMA_TX_CH_NUM 21 51 #define KS2_NETCP_PDMA_RX_BASE 0x24188000 52 #define KS2_NETCP_PDMA_RX_CH_NUM 91 53 #define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 54 #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000 55 #define KS2_NETCP_PDMA_RX_FLOW_NUM 96 56 #define KS2_NETCP_PDMA_TX_SND_QUEUE 896 57 58 /* NETCP */ 59 #define KS2_NETCP_BASE 0x24000000 60 61 #endif 62
