1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd 4 * Copyright (c) 2016 Andreas Frber 5 */ 6 7 #include <common.h> 8 #include <asm/armv8/mmu.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/cru_rk3368.h> 12 #include <asm/arch/grf_rk3368.h> 13 #include <syscon.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #define IMEM_BASE 0xFF8C0000 18 19 /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */ 20 #define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4) 21 #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28) 22 #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12) 23 /* exsram may using by mcu to accessing dram(0x0-0x20000000) */ 24 #define MCU_EXSRAM_BASE (0) 25 #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28) 26 #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12) 27 /* experi no used, reserved value = 0 */ 28 #define MCU_EXPERI_BASE (0) 29 #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28) 30 #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12) 31 32 static struct mm_region rk3368_mem_map[] = { 33 { 34 .virt = 0x0UL, 35 .phys = 0x0UL, 36 .size = 0x80000000UL, 37 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 38 PTE_BLOCK_INNER_SHARE 39 }, { 40 .virt = 0xf0000000UL, 41 .phys = 0xf0000000UL, 42 .size = 0x10000000UL, 43 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 44 PTE_BLOCK_NON_SHARE | 45 PTE_BLOCK_PXN | PTE_BLOCK_UXN 46 }, { 47 /* List terminator */ 48 0, 49 } 50 }; 51 52 struct mm_region *mem_map = rk3368_mem_map; 53 54 int dram_init_banksize(void) 55 { 56 size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); 57 58 /* Reserve 0x200000 for ATF bl31 */ 59 gd->bd->bi_dram[0].start = 0x200000; 60 gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; 61 62 return 0; 63 } 64 65 #ifdef CONFIG_ARCH_EARLY_INIT_R 66 static int mcu_init(void) 67 { 68 struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 69 struct rk3368_cru *cru = rockchip_get_cru(); 70 71 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK, 72 MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT); 73 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK, 74 MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT); 75 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK, 76 MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT); 77 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK, 78 MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT); 79 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK, 80 MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT); 81 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK, 82 MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT); 83 84 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, 85 (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) | 86 (5 << MCU_CLK_DIV_SHIFT)); 87 88 /* mcu dereset, for start running */ 89 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK); 90 91 return 0; 92 } 93 94 int arch_early_init_r(void) 95 { 96 return mcu_init(); 97 } 98 #endif 99
