1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Qualcomm APQ8916 sysmap 4 * 5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski (at) gmail.com> 6 */ 7 #ifndef _MACH_SYSMAP_APQ8016_H 8 #define _MACH_SYSMAP_APQ8016_H 9 10 #define GICD_BASE (0x0b000000) 11 #define GICC_BASE (0x0a20c000) 12 13 /* Clocks: (from CLK_CTL_BASE) */ 14 #define GPLL0_STATUS (0x2101C) 15 #define APCS_GPLL_ENA_VOTE (0x45000) 16 #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) 17 18 #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) 19 #define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) 20 #define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) 21 #define SDCC_M(n) ((n * 0x1000) + 0x4100C) 22 #define SDCC_N(n) ((n * 0x1000) + 0x41010) 23 #define SDCC_D(n) ((n * 0x1000) + 0x41014) 24 #define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) 25 #define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) 26 27 /* BLSP1 AHB clock (root clock for BLSP) */ 28 #define BLSP1_AHB_CBCR 0x1008 29 30 /* Uart clock control registers */ 31 #define BLSP1_UART2_BCR (0x3028) 32 #define BLSP1_UART2_APPS_CBCR (0x302C) 33 #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) 34 #define BLSP1_UART2_APPS_CFG_RCGR (0x3038) 35 #define BLSP1_UART2_APPS_M (0x303C) 36 #define BLSP1_UART2_APPS_N (0x3040) 37 #define BLSP1_UART2_APPS_D (0x3044) 38 39 #endif 40
