1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Altera SoCFPGA common board code 4 * 5 * Copyright (C) 2015 Marek Vasut <marex (at) denx.de> 6 */ 7 8 #include <common.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <asm/arch/reset_manager.h> 12 #include <asm/arch/clock_manager.h> 13 #include <asm/arch/misc.h> 14 #include <asm/io.h> 15 16 #include <usb.h> 17 #include <usb/dwc2_udc.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 void s_init(void) {} 22 23 /* 24 * Miscellaneous platform dependent initialisations 25 */ 26 int board_init(void) 27 { 28 /* Address of boot parameters for ATAG (if ATAG is used) */ 29 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 30 31 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 32 /* configuring the clock based on handoff */ 33 cm_basic_init(gd->fdt_blob); 34 35 /* Add device descriptor to FPGA device table */ 36 socfpga_fpga_add(); 37 #endif 38 39 return 0; 40 } 41 42 int dram_init_banksize(void) 43 { 44 fdtdec_setup_memory_banksize(); 45 46 return 0; 47 } 48 49 #ifdef CONFIG_USB_GADGET 50 struct dwc2_plat_otg_data socfpga_otg_data = { 51 .usb_gusbcfg = 0x1417, 52 }; 53 54 int board_usb_init(int index, enum usb_init_type init) 55 { 56 int node[2], count; 57 fdt_addr_t addr; 58 59 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", 60 COMPAT_ALTERA_SOCFPGA_DWC2USB, 61 node, 2); 62 if (count <= 0) /* No controller found. */ 63 return 0; 64 65 addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); 66 if (addr == FDT_ADDR_T_NONE) { 67 printf("UDC Controller has no 'reg' property!\n"); 68 return -EINVAL; 69 } 70 71 /* Patch the address from OF into the controller pdata. */ 72 socfpga_otg_data.regs_otg = addr; 73 74 return dwc2_udc_probe(&socfpga_otg_data); 75 } 76 77 int g_dnl_board_usb_cable_connected(void) 78 { 79 return 1; 80 } 81 #endif 82
