1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2017 Intel Corporation <www.intel.com> 4 * All rights reserved. 5 */ 6 7 #ifndef _FPGA_MANAGER_ARRIA10_H_ 8 #define _FPGA_MANAGER_ARRIA10_H_ 9 10 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) 11 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) 12 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) 13 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) 14 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) 15 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) 16 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) 17 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7) 18 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8) 19 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9) 20 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10) 21 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) 22 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) 23 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) 24 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) 25 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) 26 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) 27 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ 28 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\ 29 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\ 30 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK) 31 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24) 32 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25) 33 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28) 34 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29) 35 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16 36 37 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0) 38 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1) 39 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2) 40 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8) 41 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16) 42 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24) 43 44 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0) 45 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) 46 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) 47 48 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) 49 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) 50 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 51 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) 52 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 53 54 #ifndef __ASSEMBLY__ 55 56 struct socfpga_fpga_manager { 57 u32 _pad_0x0_0x7[2]; 58 u32 dclkcnt; 59 u32 dclkstat; 60 u32 gpo; 61 u32 gpi; 62 u32 misci; 63 u32 _pad_0x1c_0x2f[5]; 64 u32 emr_data0; 65 u32 emr_data1; 66 u32 emr_data2; 67 u32 emr_data3; 68 u32 emr_data4; 69 u32 emr_data5; 70 u32 emr_valid; 71 u32 emr_en; 72 u32 jtag_config; 73 u32 jtag_status; 74 u32 jtag_kick; 75 u32 _pad_0x5c_0x5f; 76 u32 jtag_data_w; 77 u32 jtag_data_r; 78 u32 _pad_0x68_0x6f[2]; 79 u32 imgcfg_ctrl_00; 80 u32 imgcfg_ctrl_01; 81 u32 imgcfg_ctrl_02; 82 u32 _pad_0x7c_0x7f; 83 u32 imgcfg_stat; 84 u32 intr_masked_status; 85 u32 intr_mask; 86 u32 intr_polarity; 87 u32 dma_config; 88 u32 imgcfg_fifo_status; 89 }; 90 91 /* Functions */ 92 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); 93 int fpgamgr_program_finish(void); 94 int is_fpgamgr_user_mode(void); 95 int fpgamgr_wait_early_user_mode(void); 96 97 #endif /* __ASSEMBLY__ */ 98 99 #endif /* _FPGA_MANAGER_ARRIA10_H_ */ 100
