1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2010-2015 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7 /* Tegra114 Clock control functions */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/sysctr.h> 13 #include <asm/arch/tegra.h> 14 #include <asm/arch-tegra/clk_rst.h> 15 #include <asm/arch-tegra/timer.h> 16 #include <div64.h> 17 #include <fdtdec.h> 18 19 /* 20 * Clock types that we can use as a source. The Tegra114 has muxes for the 21 * peripheral clocks, and in most cases there are four options for the clock 22 * source. This gives us a clock 'type' and exploits what commonality exists 23 * in the device. 24 * 25 * Letters are obvious, except for T which means CLK_M, and S which means the 26 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the 27 * datasheet) and PLL_M are different things. The former is the basic 28 * clock supplied to the SOC from an external oscillator. The latter is the 29 * memory clock PLL. 30 * 31 * See definitions in clock_id in the header file. 32 */ 33 enum clock_type_id { 34 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ 35 CLOCK_TYPE_MCPA, /* and so on */ 36 CLOCK_TYPE_MCPT, 37 CLOCK_TYPE_PCM, 38 CLOCK_TYPE_PCMT, 39 CLOCK_TYPE_PCMT16, 40 CLOCK_TYPE_PDCT, 41 CLOCK_TYPE_ACPT, 42 CLOCK_TYPE_ASPTE, 43 CLOCK_TYPE_PMDACD2T, 44 CLOCK_TYPE_PCST, 45 46 CLOCK_TYPE_COUNT, 47 CLOCK_TYPE_NONE = -1, /* invalid clock type */ 48 }; 49 50 enum { 51 CLOCK_MAX_MUX = 8 /* number of source options for each clock */ 52 }; 53 54 /* 55 * Clock source mux for each clock type. This just converts our enum into 56 * a list of mux sources for use by the code. 57 * 58 * Note: 59 * The extra column in each clock source array is used to store the mask 60 * bits in its register for the source. 61 */ 62 #define CLK(x) CLOCK_ID_ ## x 63 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { 64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC), 65 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 66 MASK_BITS_31_30}, 67 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), 68 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 69 MASK_BITS_31_30}, 70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 71 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 72 MASK_BITS_31_30}, 73 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE), 74 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 75 MASK_BITS_31_30}, 76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), 77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 78 MASK_BITS_31_30}, 79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), 80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 81 MASK_BITS_31_30}, 82 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), 83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 84 MASK_BITS_31_30}, 85 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 87 MASK_BITS_31_30}, 88 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), 89 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), 90 MASK_BITS_31_29}, 91 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), 92 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), 93 MASK_BITS_31_29}, 94 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), 95 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 96 MASK_BITS_31_28} 97 }; 98 99 /* 100 * Clock type for each peripheral clock source. We put the name in each 101 * record just so it is easy to match things up 102 */ 103 #define TYPE(name, type) type 104 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { 105 /* 0x00 */ 106 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), 107 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), 108 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), 109 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM), 110 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */ 111 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 112 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT), 113 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT), 114 115 /* 0x08 */ 116 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 117 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16), 118 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16), 119 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 120 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 121 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT), 122 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), 123 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), 124 125 /* 0x10 */ 126 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT), 127 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 128 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), 129 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 130 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT), 131 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT), 132 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA), 133 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA), 134 135 /* 0x18 */ 136 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT), 137 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT), 138 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT), 139 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA), 140 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA), 141 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */ 142 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT), 143 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT), 144 145 /* 0x20 */ 146 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA), 147 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 148 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT), 149 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T), 150 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 151 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT), 152 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16), 153 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT), 154 155 /* 0x28 */ 156 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT), 157 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 158 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), 159 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 160 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 161 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT), 162 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16), 163 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT), 164 165 /* 0x30 */ 166 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT), 167 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT), 168 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT), 169 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT), 170 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT), 171 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT), 172 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), 173 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 174 175 /* 0x38h */ /* Jumps to reg offset 0x3B0h */ 176 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA), 177 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT), 178 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */ 179 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), 180 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), 181 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16), 182 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT), 183 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT), 184 185 /* 0x40 */ 186 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT), 187 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 188 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT), 189 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT), 190 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT), 191 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT), 192 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */ 193 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), 194 195 /* 0x48 */ 196 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), 197 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), 198 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT), 199 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */ 200 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), 201 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT), 202 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 203 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 204 205 /* 0x50 */ 206 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 207 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 208 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 209 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 210 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */ 211 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), 212 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT), 213 }; 214 215 /* 216 * This array translates a periph_id to a periphc_internal_id 217 * 218 * Not present/matched up: 219 * uint vi_sensor; _VI_SENSOR_0, 0x1A8 220 * SPDIF - which is both 0x08 and 0x0c 221 * 222 */ 223 #define NONE(name) (-1) 224 #define OFFSET(name, value) PERIPHC_ ## name 225 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { 226 /* Low word: 31:0 */ 227 NONE(CPU), 228 NONE(COP), 229 NONE(TRIGSYS), 230 NONE(RESERVED3), 231 NONE(RTC), 232 NONE(TMR), 233 PERIPHC_UART1, 234 PERIPHC_UART2, /* and vfir 0x68 */ 235 236 /* 8 */ 237 NONE(GPIO), 238 PERIPHC_SDMMC2, 239 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */ 240 PERIPHC_I2S1, 241 PERIPHC_I2C1, 242 PERIPHC_NDFLASH, 243 PERIPHC_SDMMC1, 244 PERIPHC_SDMMC4, 245 246 /* 16 */ 247 NONE(RESERVED16), 248 PERIPHC_PWM, 249 PERIPHC_I2S2, 250 PERIPHC_EPP, 251 PERIPHC_VI, 252 PERIPHC_G2D, 253 NONE(USBD), 254 NONE(ISP), 255 256 /* 24 */ 257 PERIPHC_G3D, 258 NONE(RESERVED25), 259 PERIPHC_DISP2, 260 PERIPHC_DISP1, 261 PERIPHC_HOST1X, 262 NONE(VCP), 263 PERIPHC_I2S0, 264 NONE(CACHE2), 265 266 /* Middle word: 63:32 */ 267 NONE(MEM), 268 NONE(AHBDMA), 269 NONE(APBDMA), 270 NONE(RESERVED35), 271 NONE(RESERVED36), 272 NONE(STAT_MON), 273 NONE(RESERVED38), 274 NONE(RESERVED39), 275 276 /* 40 */ 277 NONE(KFUSE), 278 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */ 279 PERIPHC_NOR, 280 NONE(RESERVED43), 281 PERIPHC_SBC2, 282 NONE(RESERVED45), 283 PERIPHC_SBC3, 284 PERIPHC_I2C5, 285 286 /* 48 */ 287 NONE(DSI), 288 PERIPHC_TVO, /* also CVE 0x40 */ 289 PERIPHC_MIPI, 290 PERIPHC_HDMI, 291 NONE(CSI), 292 PERIPHC_TVDAC, 293 PERIPHC_I2C2, 294 PERIPHC_UART3, 295 296 /* 56 */ 297 NONE(RESERVED56), 298 PERIPHC_EMC, 299 NONE(USB2), 300 NONE(USB3), 301 PERIPHC_MPE, 302 PERIPHC_VDE, 303 NONE(BSEA), 304 NONE(BSEV), 305 306 /* Upper word 95:64 */ 307 PERIPHC_SPEEDO, 308 PERIPHC_UART4, 309 PERIPHC_UART5, 310 PERIPHC_I2C3, 311 PERIPHC_SBC4, 312 PERIPHC_SDMMC3, 313 NONE(PCIE), 314 PERIPHC_OWR, 315 316 /* 72 */ 317 NONE(AFI), 318 PERIPHC_CSITE, 319 NONE(PCIEXCLK), 320 NONE(AVPUCQ), 321 NONE(RESERVED76), 322 NONE(RESERVED77), 323 NONE(RESERVED78), 324 NONE(DTV), 325 326 /* 80 */ 327 PERIPHC_NANDSPEED, 328 PERIPHC_I2CSLOW, 329 NONE(DSIB), 330 NONE(RESERVED83), 331 NONE(IRAMA), 332 NONE(IRAMB), 333 NONE(IRAMC), 334 NONE(IRAMD), 335 336 /* 88 */ 337 NONE(CRAM2), 338 NONE(RESERVED89), 339 NONE(MDOUBLER), 340 NONE(RESERVED91), 341 NONE(SUSOUT), 342 NONE(RESERVED93), 343 NONE(RESERVED94), 344 NONE(RESERVED95), 345 346 /* V word: 31:0 */ 347 NONE(CPUG), 348 NONE(CPULP), 349 PERIPHC_G3D2, 350 PERIPHC_MSELECT, 351 PERIPHC_TSENSOR, 352 PERIPHC_I2S3, 353 PERIPHC_I2S4, 354 PERIPHC_I2C4, 355 356 /* 08 */ 357 PERIPHC_SBC5, 358 PERIPHC_SBC6, 359 PERIPHC_AUDIO, 360 NONE(APBIF), 361 PERIPHC_DAM0, 362 PERIPHC_DAM1, 363 PERIPHC_DAM2, 364 PERIPHC_HDA2CODEC2X, 365 366 /* 16 */ 367 NONE(ATOMICS), 368 NONE(RESERVED17), 369 NONE(RESERVED18), 370 NONE(RESERVED19), 371 NONE(RESERVED20), 372 NONE(RESERVED21), 373 NONE(RESERVED22), 374 PERIPHC_ACTMON, 375 376 /* 24 */ 377 NONE(RESERVED24), 378 NONE(RESERVED25), 379 NONE(RESERVED26), 380 NONE(RESERVED27), 381 PERIPHC_SATA, 382 PERIPHC_HDA, 383 NONE(RESERVED30), 384 NONE(RESERVED31), 385 386 /* W word: 31:0 */ 387 NONE(HDA2HDMICODEC), 388 NONE(RESERVED1_SATACOLD), 389 NONE(RESERVED2_PCIERX0), 390 NONE(RESERVED3_PCIERX1), 391 NONE(RESERVED4_PCIERX2), 392 NONE(RESERVED5_PCIERX3), 393 NONE(RESERVED6_PCIERX4), 394 NONE(RESERVED7_PCIERX5), 395 396 /* 40 */ 397 NONE(CEC), 398 NONE(PCIE2_IOBIST), 399 NONE(EMC_IOBIST), 400 NONE(HDMI_IOBIST), 401 NONE(SATA_IOBIST), 402 NONE(MIPI_IOBIST), 403 NONE(EMC1_IOBIST), 404 NONE(XUSB), 405 406 /* 48 */ 407 NONE(CILAB), 408 NONE(CILCD), 409 NONE(CILE), 410 NONE(DSIA_LP), 411 NONE(DSIB_LP), 412 NONE(RESERVED21_ENTROPY), 413 NONE(RESERVED22_W), 414 NONE(RESERVED23_W), 415 416 /* 56 */ 417 NONE(RESERVED24_W), 418 NONE(AMX0), 419 NONE(ADX0), 420 NONE(DVFS), 421 NONE(XUSB_SS), 422 NONE(EMC_DLL), 423 NONE(MC1), 424 NONE(EMC1), 425 }; 426 427 /* 428 * PLL divider shift/mask tables for all PLL IDs. 429 */ 430 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { 431 /* 432 * T114: some deviations from T2x/T30. 433 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) 434 * If lock_ena or lock_det are >31, they're not used in that PLL. 435 */ 436 437 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, 438 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ 439 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 440 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ 441 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 442 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ 443 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 444 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */ 445 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01, 446 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */ 447 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 448 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ 449 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, 450 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ 451 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 452 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ 453 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 454 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ 455 }; 456 457 /* 458 * Get the oscillator frequency, from the corresponding hardware configuration 459 * field. Note that T30/T114 support 3 new higher freqs, but we map back 460 * to the old T20 freqs. Support for the higher oscillators is TBD. 461 */ 462 enum clock_osc_freq clock_get_osc_freq(void) 463 { 464 struct clk_rst_ctlr *clkrst = 465 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 466 u32 reg; 467 468 reg = readl(&clkrst->crc_osc_ctrl); 469 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; 470 471 if (reg & 1) /* one of the newer freqs */ 472 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg); 473 474 return reg >> 2; /* Map to most common (T20) freqs */ 475 } 476 477 /* Returns a pointer to the clock source register for a peripheral */ 478 u32 *get_periph_source_reg(enum periph_id periph_id) 479 { 480 struct clk_rst_ctlr *clkrst = 481 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 482 enum periphc_internal_id internal_id; 483 484 /* Coresight is a special case */ 485 if (periph_id == PERIPH_ID_CSI) 486 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; 487 488 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); 489 internal_id = periph_id_to_internal_id[periph_id]; 490 assert(internal_id != -1); 491 if (internal_id >= PERIPHC_VW_FIRST) { 492 internal_id -= PERIPHC_VW_FIRST; 493 return &clkrst->crc_clk_src_vw[internal_id]; 494 } else 495 return &clkrst->crc_clk_src[internal_id]; 496 } 497 498 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, 499 int *divider_bits, int *type) 500 { 501 enum periphc_internal_id internal_id; 502 503 if (!clock_periph_id_isvalid(periph_id)) 504 return -1; 505 506 internal_id = periph_id_to_internal_id[periph_id]; 507 if (!periphc_internal_id_isvalid(internal_id)) 508 return -1; 509 510 *type = clock_periph_type[internal_id]; 511 if (!clock_type_id_isvalid(*type)) 512 return -1; 513 514 *mux_bits = clock_source[*type][CLOCK_MAX_MUX]; 515 516 if (*type == CLOCK_TYPE_PCMT16) 517 *divider_bits = 16; 518 else 519 *divider_bits = 8; 520 521 return 0; 522 } 523 524 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) 525 { 526 enum periphc_internal_id internal_id; 527 int type; 528 529 if (!clock_periph_id_isvalid(periph_id)) 530 return CLOCK_ID_NONE; 531 532 internal_id = periph_id_to_internal_id[periph_id]; 533 if (!periphc_internal_id_isvalid(internal_id)) 534 return CLOCK_ID_NONE; 535 536 type = clock_periph_type[internal_id]; 537 if (!clock_type_id_isvalid(type)) 538 return CLOCK_ID_NONE; 539 540 return clock_source[type][source]; 541 } 542 543 /** 544 * Given a peripheral ID and the required source clock, this returns which 545 * value should be programmed into the source mux for that peripheral. 546 * 547 * There is special code here to handle the one source type with 5 sources. 548 * 549 * @param periph_id peripheral to start 550 * @param source PLL id of required parent clock 551 * @param mux_bits Set to number of bits in mux register: 2 or 4 552 * @param divider_bits Set to number of divider bits (8 or 16) 553 * @return mux value (0-4, or -1 if not found) 554 */ 555 int get_periph_clock_source(enum periph_id periph_id, 556 enum clock_id parent, int *mux_bits, int *divider_bits) 557 { 558 enum clock_type_id type; 559 int mux, err; 560 561 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type); 562 assert(!err); 563 564 for (mux = 0; mux < CLOCK_MAX_MUX; mux++) 565 if (clock_source[type][mux] == parent) 566 return mux; 567 568 /* if we get here, either us or the caller has made a mistake */ 569 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, 570 parent); 571 return -1; 572 } 573 574 void clock_set_enable(enum periph_id periph_id, int enable) 575 { 576 struct clk_rst_ctlr *clkrst = 577 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 578 u32 *clk; 579 u32 reg; 580 581 /* Enable/disable the clock to this peripheral */ 582 assert(clock_periph_id_isvalid(periph_id)); 583 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) 584 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; 585 else 586 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; 587 reg = readl(clk); 588 if (enable) 589 reg |= PERIPH_MASK(periph_id); 590 else 591 reg &= ~PERIPH_MASK(periph_id); 592 writel(reg, clk); 593 } 594 595 void reset_set_enable(enum periph_id periph_id, int enable) 596 { 597 struct clk_rst_ctlr *clkrst = 598 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 599 u32 *reset; 600 u32 reg; 601 602 /* Enable/disable reset to the peripheral */ 603 assert(clock_periph_id_isvalid(periph_id)); 604 if (periph_id < PERIPH_ID_VW_FIRST) 605 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; 606 else 607 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; 608 reg = readl(reset); 609 if (enable) 610 reg |= PERIPH_MASK(periph_id); 611 else 612 reg &= ~PERIPH_MASK(periph_id); 613 writel(reg, reset); 614 } 615 616 #if CONFIG_IS_ENABLED(OF_CONTROL) 617 /* 618 * Convert a device tree clock ID to our peripheral ID. They are mostly 619 * the same but we are very cautious so we check that a valid clock ID is 620 * provided. 621 * 622 * @param clk_id Clock ID according to tegra114 device tree binding 623 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 624 */ 625 enum periph_id clk_id_to_periph_id(int clk_id) 626 { 627 if (clk_id > PERIPH_ID_COUNT) 628 return PERIPH_ID_NONE; 629 630 switch (clk_id) { 631 case PERIPH_ID_RESERVED3: 632 case PERIPH_ID_RESERVED16: 633 case PERIPH_ID_RESERVED24: 634 case PERIPH_ID_RESERVED35: 635 case PERIPH_ID_RESERVED43: 636 case PERIPH_ID_RESERVED45: 637 case PERIPH_ID_RESERVED56: 638 case PERIPH_ID_RESERVED76: 639 case PERIPH_ID_RESERVED77: 640 case PERIPH_ID_RESERVED78: 641 case PERIPH_ID_RESERVED83: 642 case PERIPH_ID_RESERVED89: 643 case PERIPH_ID_RESERVED91: 644 case PERIPH_ID_RESERVED93: 645 case PERIPH_ID_RESERVED94: 646 case PERIPH_ID_RESERVED95: 647 return PERIPH_ID_NONE; 648 default: 649 return clk_id; 650 } 651 } 652 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 653 654 void clock_early_init(void) 655 { 656 struct clk_rst_ctlr *clkrst = 657 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 658 struct clk_pll_info *pllinfo; 659 u32 data; 660 661 tegra30_set_up_pllp(); 662 663 /* clear IDDQ before accessing any other PLLC registers */ 664 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; 665 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); 666 udelay(2); 667 668 /* 669 * PLLC output frequency set to 600Mhz 670 * PLLD output frequency set to 925Mhz 671 */ 672 switch (clock_get_osc_freq()) { 673 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ 674 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); 675 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); 676 break; 677 678 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ 679 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); 680 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); 681 break; 682 683 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ 684 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); 685 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); 686 break; 687 case CLOCK_OSC_FREQ_19_2: 688 default: 689 /* 690 * These are not supported. It is too early to print a 691 * message and the UART likely won't work anyway due to the 692 * oscillator being wrong. 693 */ 694 break; 695 } 696 697 /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */ 698 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); 699 700 /* PLLC_MISC: Set LOCK_ENABLE */ 701 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; 702 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); 703 udelay(2); 704 705 /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */ 706 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; 707 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); 708 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); 709 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); 710 udelay(2); 711 } 712 713 void arch_timer_init(void) 714 { 715 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; 716 u32 freq, val; 717 718 freq = clock_get_rate(CLOCK_ID_CLK_M); 719 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); 720 721 /* ARM CNTFRQ */ 722 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); 723 724 /* Only T114 has the System Counter regs */ 725 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); 726 writel(freq, &sysctr->cntfid0); 727 728 val = readl(&sysctr->cntcr); 729 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; 730 writel(val, &sysctr->cntcr); 731 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); 732 } 733 734 struct periph_clk_init periph_clk_init_table[] = { 735 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, 736 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, 737 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH }, 738 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH }, 739 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, 740 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, 741 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, 742 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, 743 { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH }, 744 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, 745 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, 746 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, 747 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH }, 748 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ }, 749 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH }, 750 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH }, 751 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH }, 752 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH }, 753 { PERIPH_ID_I2C5, CLOCK_ID_PERIPH }, 754 { -1, }, 755 }; 756
