1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2013-2014 Panasonic Corporation 4 * Copyright (C) 2015-2016 Socionext Inc. 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/io.h> 9 10 #include "../init.h" 11 #include "../sc-regs.h" 12 13 int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) 14 { 15 u32 tmp; 16 /* 17 * Set DPLL SSC parameters for DPLLCTRL3 18 * [23] DIVN_TEST 0x1 19 * [22:16] DIVN 0x50 20 * [10] FREFSEL_TEST 0x1 21 * [9:8] FREFSEL 0x2 22 * [4] ICPD_TEST 0x1 23 * [3:0] ICPD 0xb 24 */ 25 tmp = readl(SC_DPLLCTRL3); 26 tmp &= ~0x00ff0717; 27 tmp |= 0x00d0061b; 28 writel(tmp, SC_DPLLCTRL3); 29 30 /* 31 * Set DPLL SSC parameters for DPLLCTRL 32 * <-1%> <-2%> 33 * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) 34 * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) 35 */ 36 tmp = readl(SC_DPLLCTRL); 37 tmp &= ~0x3ff07fff; 38 #ifdef DPLL_SSC_RATE_1PER 39 tmp |= 0x084018bf; 40 #else 41 tmp |= 0x084031a6; 42 #endif 43 writel(tmp, SC_DPLLCTRL); 44 45 /* 46 * Set DPLL SSC parameters for DPLLCTRL2 47 * [31:29] SSC_STEP 0 48 * [27] SSC_REG_REF 1 49 * [26:20] SSC_M 79 (0x4f) 50 * [19:0] SSC_K 964689 (0xeb851) 51 */ 52 tmp = readl(SC_DPLLCTRL2); 53 tmp &= ~0xefffffff; 54 tmp |= 0x0cfeb851; 55 writel(tmp, SC_DPLLCTRL2); 56 57 /* Wait 500 usec until dpll gets stable */ 58 udelay(500); 59 60 return 0; 61 } 62
