1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * UniPhier SC (System Control) block registers for ARMv8 SoCs 4 * 5 * Copyright (C) 2016 Socionext Inc. 6 * Author: Masahiro Yamada <yamada.masahiro (at) socionext.com> 7 */ 8 9 #ifndef SC64_REGS_H 10 #define SC64_REGS_H 11 12 #define SC_BASE_ADDR 0x61840000 13 14 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) 15 #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) 16 #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) 17 #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) 18 #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) 19 #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018) 20 21 #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) 22 #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) 23 #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) 24 #define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110) 25 #define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114) 26 #define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118) 27 28 #define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000) 29 #define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004) 30 #define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008) 31 #define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080) 32 #define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084) 33 #define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088) 34 #define SC_CA_GEARUPD (1 << 0) 35 36 #endif /* SC64_REGS_H */ 37
