1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * MCF5227x Internal Memory Map 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew (at) freescale.com) 7 */ 8 9 #ifndef __MCF5227X__ 10 #define __MCF5227X__ 11 12 /* Interrupt Controller (INTC) */ 13 #define INT0_LO_RSVD0 (0) 14 #define INT0_LO_EPORT1 (1) 15 #define INT0_LO_EPORT4 (4) 16 #define INT0_LO_EPORT7 (7) 17 #define INT0_LO_EDMA_00 (8) 18 #define INT0_LO_EDMA_01 (9) 19 #define INT0_LO_EDMA_02 (10) 20 #define INT0_LO_EDMA_03 (11) 21 #define INT0_LO_EDMA_04 (12) 22 #define INT0_LO_EDMA_05 (13) 23 #define INT0_LO_EDMA_06 (14) 24 #define INT0_LO_EDMA_07 (15) 25 #define INT0_LO_EDMA_08 (16) 26 #define INT0_LO_EDMA_09 (17) 27 #define INT0_LO_EDMA_10 (18) 28 #define INT0_LO_EDMA_11 (19) 29 #define INT0_LO_EDMA_12 (20) 30 #define INT0_LO_EDMA_13 (21) 31 #define INT0_LO_EDMA_14 (22) 32 #define INT0_LO_EDMA_15 (23) 33 #define INT0_LO_EDMA_ERR (24) 34 #define INT0_LO_SCM_CWIC (25) 35 #define INT0_LO_UART0 (26) 36 #define INT0_LO_UART1 (27) 37 #define INT0_LO_UART2 (28) 38 #define INT0_LO_I2C (30) 39 #define INT0_LO_DSPI (31) 40 #define INT0_HI_DTMR0 (32) 41 #define INT0_HI_DTMR1 (33) 42 #define INT0_HI_DTMR2 (34) 43 #define INT0_HI_DTMR3 (35) 44 #define INT0_HI_SCMIR (62) 45 #define INT0_HI_RTC_ISR (63) 46 47 #define INT1_HI_CAN_BOFFINT (1) 48 #define INT1_HI_CAN_ERRINT (3) 49 #define INT1_HI_CAN_BUF0I (4) 50 #define INT1_HI_CAN_BUF1I (5) 51 #define INT1_HI_CAN_BUF2I (6) 52 #define INT1_HI_CAN_BUF3I (7) 53 #define INT1_HI_CAN_BUF4I (8) 54 #define INT1_HI_CAN_BUF5I (9) 55 #define INT1_HI_CAN_BUF6I (10) 56 #define INT1_HI_CAN_BUF7I (11) 57 #define INT1_HI_CAN_BUF8I (12) 58 #define INT1_HI_CAN_BUF9I (13) 59 #define INT1_HI_CAN_BUF10I (14) 60 #define INT1_HI_CAN_BUF11I (15) 61 #define INT1_HI_CAN_BUF12I (16) 62 #define INT1_HI_CAN_BUF13I (17) 63 #define INT1_HI_CAN_BUF14I (18) 64 #define INT1_HI_CAN_BUF15I (19) 65 #define INT1_HI_PIT0_PIF (43) 66 #define INT1_HI_PIT1_PIF (44) 67 #define INT1_HI_USBOTG_STS (47) 68 #define INT1_HI_SSI_ISR (49) 69 #define INT1_HI_PWM_INT (50) 70 #define INT1_HI_LCDC_ISR (51) 71 #define INT1_HI_CCM_UOCSR (53) 72 #define INT1_HI_DSPI_EOQF (54) 73 #define INT1_HI_DSPI_TFFF (55) 74 #define INT1_HI_DSPI_TCF (56) 75 #define INT1_HI_DSPI_TFUF (57) 76 #define INT1_HI_DSPI_RFDF (58) 77 #define INT1_HI_DSPI_RFOF (59) 78 #define INT1_HI_DSPI_RFOF_TFUF (60) 79 #define INT1_HI_TOUCH_ADC (61) 80 #define INT1_HI_PLL_LOCKS (62) 81 82 /********************************************************************* 83 * Reset Controller Module (RCM) 84 *********************************************************************/ 85 86 /* Bit definitions and macros for RCR */ 87 #define RCM_RCR_FRCRSTOUT (0x40) 88 #define RCM_RCR_SOFTRST (0x80) 89 90 /* Bit definitions and macros for RSR */ 91 #define RCM_RSR_LOL (0x01) 92 #define RCM_RSR_WDR_CORE (0x02) 93 #define RCM_RSR_EXT (0x04) 94 #define RCM_RSR_POR (0x08) 95 #define RCM_RSR_SOFT (0x20) 96 97 /********************************************************************* 98 * Chip Configuration Module (CCM) 99 *********************************************************************/ 100 101 /* Bit definitions and macros for CCR */ 102 #define CCM_CCR_DRAMSEL (0x0100) 103 #define CCM_CCR_CSC_UNMASK (0xFF3F) 104 #define CCM_CCR_CSC_FBCS5_CS4 (0x00C0) 105 #define CCM_CCR_CSC_FBCS5_A22 (0x0080) 106 #define CCM_CCR_CSC_FB_A23_A22 (0x0040) 107 #define CCM_CCR_LIMP (0x0020) 108 #define CCM_CCR_LOAD (0x0010) 109 #define CCM_CCR_BOOTPS_UNMASK (0xFFF3) 110 #define CCM_CCR_BOOTPS_PS16 (0x0008) 111 #define CCM_CCR_BOOTPS_PS8 (0x0004) 112 #define CCM_CCR_BOOTPS_PS32 (0x0000) 113 #define CCM_CCR_OSCMODE_OSCBYPASS (0x0002) 114 115 /* Bit definitions and macros for RCON */ 116 #define CCM_RCON_CSC_UNMASK (0xFF3F) 117 #define CCM_RCON_CSC_FBCS5_CS4 (0x00C0) 118 #define CCM_RCON_CSC_FBCS5_A22 (0x0080) 119 #define CCM_RCON_CSC_FB_A23_A22 (0x0040) 120 #define CCM_RCON_LIMP (0x0020) 121 #define CCM_RCON_LOAD (0x0010) 122 #define CCM_RCON_BOOTPS_UNMASK (0xFFF3) 123 #define CCM_RCON_BOOTPS_PS16 (0x0008) 124 #define CCM_RCON_BOOTPS_PS8 (0x0004) 125 #define CCM_RCON_BOOTPS_PS32 (0x0000) 126 #define CCM_RCON_OSCMODE_OSCBYPASS (0x0002) 127 128 /* Bit definitions and macros for CIR */ 129 #define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) 130 #define CCM_CIR_PRN(x) ((x) & 0x003F) 131 #define CCM_CIR_PIN_MCF52277 (0x0000) 132 133 /* Bit definitions and macros for MISCCR */ 134 #define CCM_MISCCR_RTCSRC (0x4000) 135 #define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */ 136 #define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ 137 138 #define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */ 139 #define CCM_MISCCR_BMT_65536 (0) 140 #define CCM_MISCCR_BMT_32768 (1) 141 #define CCM_MISCCR_BMT_16384 (2) 142 #define CCM_MISCCR_BMT_8192 (3) 143 #define CCM_MISCCR_BMT_4096 (4) 144 #define CCM_MISCCR_BMT_2048 (5) 145 #define CCM_MISCCR_BMT_1024 (6) 146 #define CCM_MISCCR_BMT_512 (7) 147 148 #define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ 149 #define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ 150 #define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ 151 #define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ 152 #define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */ 153 #define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */ 154 #define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ 155 156 /* Bit definitions and macros for CDR */ 157 #define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12) 158 #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */ 159 #define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */ 160 161 /* Bit definitions and macros for UOCSR */ 162 #define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */ 163 #define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */ 164 #define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */ 165 #define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */ 166 #define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */ 167 #define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ 168 #define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ 169 #define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ 170 #define CCM_UOCSR_SEND (0x0010) /* Session end */ 171 #define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ 172 #define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */ 173 #define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */ 174 175 /********************************************************************* 176 * General Purpose I/O Module (GPIO) 177 *********************************************************************/ 178 /* Bit definitions and macros for PAR_BE */ 179 #define GPIO_PAR_BE_UNMASK (0x0F) 180 #define GPIO_PAR_BE_BE3_BE3 (0x08) 181 #define GPIO_PAR_BE_BE3_GPIO (0x00) 182 #define GPIO_PAR_BE_BE2_BE2 (0x04) 183 #define GPIO_PAR_BE_BE2_GPIO (0x00) 184 #define GPIO_PAR_BE_BE1_BE1 (0x02) 185 #define GPIO_PAR_BE_BE1_GPIO (0x00) 186 #define GPIO_PAR_BE_BE0_BE0 (0x01) 187 #define GPIO_PAR_BE_BE0_GPIO (0x00) 188 189 /* Bit definitions and macros for PAR_CS */ 190 #define GPIO_PAR_CS_CS3 (0x10) 191 #define GPIO_PAR_CS_CS2 (0x08) 192 #define GPIO_PAR_CS_CS1_FBCS1 (0x06) 193 #define GPIO_PAR_CS_CS1_SDCS1 (0x04) 194 #define GPIO_PAR_CS_CS1_GPIO (0x00) 195 #define GPIO_PAR_CS_CS0 (0x01) 196 197 /* Bit definitions and macros for PAR_FBCTL */ 198 #define GPIO_PAR_FBCTL_OE (0x80) 199 #define GPIO_PAR_FBCTL_TA (0x40) 200 #define GPIO_PAR_FBCTL_RW (0x20) 201 #define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) 202 #define GPIO_PAR_FBCTL_TS_FBTS (0x18) 203 #define GPIO_PAR_FBCTL_TS_DMAACK (0x10) 204 #define GPIO_PAR_FBCTL_TS_GPIO (0x00) 205 206 /* Bit definitions and macros for PAR_FECI2C */ 207 #define GPIO_PAR_I2C_SCL_UNMASK (0xF3) 208 #define GPIO_PAR_I2C_SCL_SCL (0x0C) 209 #define GPIO_PAR_I2C_SCL_CANTXD (0x08) 210 #define GPIO_PAR_I2C_SCL_U2TXD (0x04) 211 #define GPIO_PAR_I2C_SCL_GPIO (0x00) 212 213 #define GPIO_PAR_I2C_SDA_UNMASK (0xFC) 214 #define GPIO_PAR_I2C_SDA_SDA (0x03) 215 #define GPIO_PAR_I2C_SDA_CANRXD (0x02) 216 #define GPIO_PAR_I2C_SDA_U2RXD (0x01) 217 #define GPIO_PAR_I2C_SDA_GPIO (0x00) 218 219 /* Bit definitions and macros for PAR_UART */ 220 #define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF) 221 #define GPIO_PAR_UART_U1CTS_U1CTS (0xC000) 222 #define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000) 223 #define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000) 224 #define GPIO_PAR_UART_U1CTS_GPIO (0x0000) 225 226 #define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF) 227 #define GPIO_PAR_UART_U1RTS_U1RTS (0x3000) 228 #define GPIO_PAR_UART_U1RTS_SSIFS (0x2000) 229 #define GPIO_PAR_UART_U1RTS_LCDPS (0x1000) 230 #define GPIO_PAR_UART_U1RTS_GPIO (0x0000) 231 232 #define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF) 233 #define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) 234 #define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800) 235 #define GPIO_PAR_UART_U1RXD_GPIO (0x0000) 236 237 #define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF) 238 #define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) 239 #define GPIO_PAR_UART_U1TXD_SSITXD (0x0200) 240 #define GPIO_PAR_UART_U1TXD_GPIO (0x0000) 241 242 #define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F) 243 #define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0) 244 #define GPIO_PAR_UART_U0CTS_T1OUT (0x0080) 245 #define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040) 246 #define GPIO_PAR_UART_U0CTS_GPIO (0x0000) 247 248 #define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF) 249 #define GPIO_PAR_UART_U0RTS_U0RTS (0x0030) 250 #define GPIO_PAR_UART_U0RTS_T1IN (0x0020) 251 #define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010) 252 #define GPIO_PAR_UART_U0RTS_GPIO (0x0000) 253 254 #define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3) 255 #define GPIO_PAR_UART_U0RXD_U0RXD (0x000C) 256 #define GPIO_PAR_UART_U0RXD_CANRX (0x0008) 257 #define GPIO_PAR_UART_U0RXD_GPIO (0x0000) 258 259 #define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC) 260 #define GPIO_PAR_UART_U0TXD_U0TXD (0x0003) 261 #define GPIO_PAR_UART_U0TXD_CANTX (0x0002) 262 #define GPIO_PAR_UART_U0TXD_GPIO (0x0000) 263 264 /* Bit definitions and macros for PAR_DSPI */ 265 #define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F) 266 #define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0) 267 #define GPIO_PAR_DSPI_PCS0_U2RTS (0x80) 268 #define GPIO_PAR_DSPI_PCS0_GPIO (0x00) 269 #define GPIO_PAR_DSPI_SIN_UNMASK (0xCF) 270 #define GPIO_PAR_DSPI_SIN_SIN (0x30) 271 #define GPIO_PAR_DSPI_SIN_U2RXD (0x20) 272 #define GPIO_PAR_DSPI_SIN_GPIO (0x00) 273 #define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3) 274 #define GPIO_PAR_DSPI_SOUT_SOUT (0x0C) 275 #define GPIO_PAR_DSPI_SOUT_U2TXD (0x08) 276 #define GPIO_PAR_DSPI_SOUT_GPIO (0x00) 277 #define GPIO_PAR_DSPI_SCK_UNMASK (0xFC) 278 #define GPIO_PAR_DSPI_SCK_SCK (0x03) 279 #define GPIO_PAR_DSPI_SCK_U2CTS (0x02) 280 #define GPIO_PAR_DSPI_SCK_GPIO (0x00) 281 282 /* Bit definitions and macros for PAR_TIMER */ 283 #define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) 284 #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) 285 #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) 286 #define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40) 287 #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) 288 #define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) 289 #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) 290 #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) 291 #define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10) 292 #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) 293 #define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) 294 #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) 295 #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) 296 #define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04) 297 #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) 298 #define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) 299 #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) 300 #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) 301 #define GPIO_PAR_TIMER_T0IN_LCDREV (0x01) 302 #define GPIO_PAR_TIMER_T0IN_GPIO (0x00) 303 304 /* Bit definitions and macros for GPIO_PAR_LCDCTL */ 305 #define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7) 306 #define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18) 307 #define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10) 308 #define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00) 309 #define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04) 310 #define GPIO_PAR_LCDCTL_LP_HSYNC (0x02) 311 #define GPIO_PAR_LCDCTL_LSCLK (0x01) 312 313 /* Bit definitions and macros for PAR_IRQ */ 314 #define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3) 315 #define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C) 316 #define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08) 317 #define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) 318 #define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC) 319 #define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03) 320 #define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02) 321 #define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01) 322 #define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) 323 324 /* Bit definitions and macros for GPIO_PAR_LCDH */ 325 #define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF) 326 #define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00) 327 #define GPIO_PAR_LCDH_LD17_LD11 (0x00000800) 328 #define GPIO_PAR_LCDH_LD17_GPIO (0x00000000) 329 330 #define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF) 331 #define GPIO_PAR_LCDH_LD16_LD16 (0x00000300) 332 #define GPIO_PAR_LCDH_LD16_LD10 (0x00000200) 333 #define GPIO_PAR_LCDH_LD16_GPIO (0x00000000) 334 335 #define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F) 336 #define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0) 337 #define GPIO_PAR_LCDH_LD15_LD9 (0x00000080) 338 #define GPIO_PAR_LCDH_LD15_GPIO (0x00000000) 339 340 #define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF) 341 #define GPIO_PAR_LCDH_LD14_LD14 (0x00000030) 342 #define GPIO_PAR_LCDH_LD14_LD8 (0x00000020) 343 #define GPIO_PAR_LCDH_LD14_GPIO (0x00000000) 344 345 #define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3) 346 #define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C) 347 #define GPIO_PAR_LCDH_LD13_CANTX (0x00000008) 348 #define GPIO_PAR_LCDH_LD13_GPIO (0x00000000) 349 350 #define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC) 351 #define GPIO_PAR_LCDH_LD12_LD12 (0x00000003) 352 #define GPIO_PAR_LCDH_LD12_CANRX (0x00000002) 353 #define GPIO_PAR_LCDH_LD12_GPIO (0x00000000) 354 355 /* Bit definitions and macros for GPIO_PAR_LCDL */ 356 #define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF) 357 #define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000) 358 #define GPIO_PAR_LCDL_LD11_LD7 (0x80000000) 359 #define GPIO_PAR_LCDL_LD11_GPIO (0x00000000) 360 361 #define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF) 362 #define GPIO_PAR_LCDL_LD10_LD10 (0x30000000) 363 #define GPIO_PAR_LCDL_LD10_LD6 (0x20000000) 364 #define GPIO_PAR_LCDL_LD10_GPIO (0x00000000) 365 366 #define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF) 367 #define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000) 368 #define GPIO_PAR_LCDL_LD9_LD5 (0x08000000) 369 #define GPIO_PAR_LCDL_LD9_GPIO (0x00000000) 370 371 #define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF) 372 #define GPIO_PAR_LCDL_LD8_LD8 (0x03000000) 373 #define GPIO_PAR_LCDL_LD8_LD4 (0x02000000) 374 #define GPIO_PAR_LCDL_LD8_GPIO (0x00000000) 375 376 #define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF) 377 #define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000) 378 #define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000) 379 #define GPIO_PAR_LCDL_LD7_GPIO (0x00000000) 380 381 #define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF) 382 #define GPIO_PAR_LCDL_LD6_LD6 (0x00300000) 383 #define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000) 384 #define GPIO_PAR_LCDL_LD6_GPIO (0x00000000) 385 386 #define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF) 387 #define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000) 388 #define GPIO_PAR_LCDL_LD5_LD3 (0x00080000) 389 #define GPIO_PAR_LCDL_LD5_GPIO (0x00000000) 390 391 #define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF) 392 #define GPIO_PAR_LCDL_LD4_LD4 (0x00030000) 393 #define GPIO_PAR_LCDL_LD4_LD2 (0x00020000) 394 #define GPIO_PAR_LCDL_LD4_GPIO (0x00000000) 395 396 #define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF) 397 #define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000) 398 #define GPIO_PAR_LCDL_LD3_LD1 (0x00008000) 399 #define GPIO_PAR_LCDL_LD3_GPIO (0x00000000) 400 401 #define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF) 402 #define GPIO_PAR_LCDL_LD2_LD2 (0x00003000) 403 #define GPIO_PAR_LCDL_LD2_LD0 (0x00002000) 404 #define GPIO_PAR_LCDL_LD2_GPIO (0x00000000) 405 406 #define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF) 407 #define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00) 408 #define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800) 409 #define GPIO_PAR_LCDL_LD1_GPIO (0x00000000) 410 411 #define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF) 412 #define GPIO_PAR_LCDL_LD0_LD0 (0x00000300) 413 #define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200) 414 #define GPIO_PAR_LCDL_LD0_GPIO (0x00000000) 415 416 /* Bit definitions and macros for MSCR_FB */ 417 #define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF) 418 #define GPIO_MSCR_FB_DUPPER_25V_33V (0x30) 419 #define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20) 420 #define GPIO_MSCR_FB_DUPPER_OD (0x10) 421 #define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00) 422 423 #define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3) 424 #define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C) 425 #define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08) 426 #define GPIO_MSCR_FB_DLOWER_OD (0x04) 427 #define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00) 428 429 #define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC) 430 #define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03) 431 #define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02) 432 #define GPIO_MSCR_FB_ADDRCTL_OD (0x01) 433 #define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00) 434 435 /* Bit definitions and macros for MSCR_SDRAM */ 436 #define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF) 437 #define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30) 438 #define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20) 439 #define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10) 440 #define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00) 441 442 #define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) 443 #define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C) 444 #define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08) 445 #define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04) 446 #define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00) 447 448 #define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) 449 #define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03) 450 #define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02) 451 #define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01) 452 #define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00) 453 454 /* Bit definitions and macros for Drive Strength Control */ 455 #define DSCR_LOAD_50PF (0x03) 456 #define DSCR_LOAD_30PF (0x02) 457 #define DSCR_LOAD_20PF (0x01) 458 #define DSCR_LOAD_10PF (0x00) 459 460 /********************************************************************* 461 * SDRAM Controller (SDRAMC) 462 *********************************************************************/ 463 464 /* Bit definitions and macros for SDMR */ 465 #define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ 466 #define SDRAMC_SDMR_CMD (0x00010000) /* Command */ 467 #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ 468 #define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ 469 #define SDRAMC_SDMR_BK_LMR (0x00000000) 470 #define SDRAMC_SDMR_BK_LEMR (0x40000000) 471 472 /* Bit definitions and macros for SDCR */ 473 #define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ 474 #define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ 475 #define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ 476 #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ 477 #define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ 478 #define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ 479 #define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ 480 #define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ 481 #define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ 482 #define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ 483 #define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ 484 #define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ 485 #define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ 486 #define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) 487 488 /* Bit definitions and macros for SDCFG1 */ 489 #define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ 490 #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ 491 #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ 492 #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ 493 #define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ 494 #define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ 495 #define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ 496 497 /* Bit definitions and macros for SDCFG2 */ 498 #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ 499 #define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ 500 #define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ 501 #define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ 502 503 /* Bit definitions and macros for SDCS group */ 504 #define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ 505 #define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ 506 #define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) 507 #define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) 508 #define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) 509 #define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) 510 #define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) 511 #define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) 512 #define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) 513 #define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) 514 #define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) 515 #define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) 516 #define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) 517 #define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) 518 #define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) 519 #define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) 520 #define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) 521 522 /********************************************************************* 523 * Phase Locked Loop (PLL) 524 *********************************************************************/ 525 526 /* Bit definitions and macros for PCR */ 527 #define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ 528 #define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */ 529 #define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */ 530 #define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ 531 #define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ 532 #define PLL_PCR_PFDR_MASK (0x000F0000) 533 #define PLL_PCR_OUTDIV5_MASK (0x000F0000) 534 #define PLL_PCR_OUTDIV3_MASK (0x00000F00) 535 #define PLL_PCR_OUTDIV2_MASK (0x000000F0) 536 #define PLL_PCR_OUTDIV1_MASK (0x0000000F) 537 538 /* Bit definitions and macros for PSR */ 539 #define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ 540 #define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ 541 #define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ 542 #define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ 543 544 /********************************************************************/ 545 546 #endif /* __MCF5227X__ */ 547
