1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew (at) freescale.com) 7 */ 8 9 #ifndef mcf547x_8x_h 10 #define mcf547x_8x_h 11 12 /********************************************************************* 13 * XLB Arbiter (XLB) 14 *********************************************************************/ 15 /* Bit definitions and macros for XARB_CFG */ 16 #define XARB_CFG_AT (0x00000002) 17 #define XARB_CFG_DT (0x00000004) 18 #define XARB_CFG_BA (0x00000008) 19 #define XARB_CFG_PM(x) (((x)&0x00000003)<<5) 20 #define XARB_CFG_SP(x) (((x)&0x00000007)<<8) 21 #define XARB_CFG_PLDIS (0x80000000) 22 23 /* Bit definitions and macros for XARB_SR */ 24 #define XARB_SR_AT (0x00000001) 25 #define XARB_SR_DT (0x00000002) 26 #define XARB_SR_BA (0x00000004) 27 #define XARB_SR_TTM (0x00000008) 28 #define XARB_SR_ECW (0x00000010) 29 #define XARB_SR_TTR (0x00000020) 30 #define XARB_SR_TTA (0x00000040) 31 #define XARB_SR_MM (0x00000080) 32 #define XARB_SR_SEA (0x00000100) 33 34 /* Bit definitions and macros for XARB_IMR */ 35 #define XARB_IMR_ATE (0x00000001) 36 #define XARB_IMR_DTE (0x00000002) 37 #define XARB_IMR_BAE (0x00000004) 38 #define XARB_IMR_TTME (0x00000008) 39 #define XARB_IMR_ECWE (0x00000010) 40 #define XARB_IMR_TTRE (0x00000020) 41 #define XARB_IMR_TTAE (0x00000040) 42 #define XARB_IMR_MME (0x00000080) 43 #define XARB_IMR_SEAE (0x00000100) 44 45 /* Bit definitions and macros for XARB_SIGCAP */ 46 #define XARB_SIGCAP_TT(x) ((x)&0x0000001F) 47 #define XARB_SIGCAP_TBST (0x00000020) 48 #define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7) 49 50 /* Bit definitions and macros for XARB_PRIEN */ 51 #define XARB_PRIEN_M0 (0x00000001) 52 #define XARB_PRIEN_M2 (0x00000004) 53 #define XARB_PRIEN_M3 (0x00000008) 54 55 /* Bit definitions and macros for XARB_PRI */ 56 #define XARB_PRI_M0P(x) (((x)&0x00000007)<<0) 57 #define XARB_PRI_M2P(x) (((x)&0x00000007)<<8) 58 #define XARB_PRI_M3P(x) (((x)&0x00000007)<<12) 59 60 /********************************************************************* 61 * General Purpose I/O (GPIO) 62 *********************************************************************/ 63 /* Bit definitions and macros for GPIO_PAR_FBCTL */ 64 #define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0) 65 #define GPIO_PAR_FBCTL_TA (0x0004) 66 #define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4) 67 #define GPIO_PAR_FBCTL_OE (0x0040) 68 #define GPIO_PAR_FBCTL_BWE0 (0x0100) 69 #define GPIO_PAR_FBCTL_BWE1 (0x0400) 70 #define GPIO_PAR_FBCTL_BWE2 (0x1000) 71 #define GPIO_PAR_FBCTL_BWE3 (0x4000) 72 #define GPIO_PAR_FBCTL_TS_GPIO (0) 73 #define GPIO_PAR_FBCTL_TS_TBST (2) 74 #define GPIO_PAR_FBCTL_TS_TS (3) 75 #define GPIO_PAR_FBCTL_RWB_GPIO (0x0000) 76 #define GPIO_PAR_FBCTL_RWB_TBST (0x0020) 77 #define GPIO_PAR_FBCTL_RWB_RWB (0x0030) 78 79 /* Bit definitions and macros for GPIO_PAR_FBCS */ 80 #define GPIO_PAR_FBCS_CS1 (0x02) 81 #define GPIO_PAR_FBCS_CS2 (0x04) 82 #define GPIO_PAR_FBCS_CS3 (0x08) 83 #define GPIO_PAR_FBCS_CS4 (0x10) 84 #define GPIO_PAR_FBCS_CS5 (0x20) 85 86 /* Bit definitions and macros for GPIO_PAR_DMA */ 87 #define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0) 88 #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2) 89 #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4) 90 #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) 91 #define GPIO_PAR_DMA_DACKx_GPIO (0) 92 #define GPIO_PAR_DMA_DACKx_TOUT (2) 93 #define GPIO_PAR_DMA_DACKx_DACK (3) 94 #define GPIO_PAR_DMA_DREQx_GPIO (0) 95 #define GPIO_PAR_DMA_DREQx_TIN (2) 96 #define GPIO_PAR_DMA_DREQx_DREQ (3) 97 98 /* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */ 99 #define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001) 100 #define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002) 101 #define GPIO_PAR_FECI2CIRQ_SCL (0x0004) 102 #define GPIO_PAR_FECI2CIRQ_SDA (0x0008) 103 #define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6) 104 #define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8) 105 #define GPIO_PAR_FECI2CIRQ_E1MII (0x0400) 106 #define GPIO_PAR_FECI2CIRQ_E17 (0x0800) 107 #define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000) 108 #define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000) 109 #define GPIO_PAR_FECI2CIRQ_E0MII (0x4000) 110 #define GPIO_PAR_FECI2CIRQ_E07 (0x8000) 111 #define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000) 112 #define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200) 113 #define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300) 114 #define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000) 115 #define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080) 116 #define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0) 117 118 /* Bit definitions and macros for GPIO_PAR_PCIBG */ 119 #define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0) 120 #define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2) 121 #define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4) 122 #define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6) 123 #define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8) 124 125 /* Bit definitions and macros for GPIO_PAR_PCIBR */ 126 #define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0) 127 #define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2) 128 #define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4) 129 #define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6) 130 #define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8) 131 132 /* Bit definitions and macros for GPIO_PAR_PSC3 */ 133 #define GPIO_PAR_PSC3_TXD3 (0x04) 134 #define GPIO_PAR_PSC3_RXD3 (0x08) 135 #define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4) 136 #define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6) 137 #define GPIO_PAR_PSC3_CTS3_GPIO (0x00) 138 #define GPIO_PAR_PSC3_CTS3_BCLK (0x80) 139 #define GPIO_PAR_PSC3_CTS3_CTS (0xC0) 140 #define GPIO_PAR_PSC3_RTS3_GPIO (0x00) 141 #define GPIO_PAR_PSC3_RTS3_FSYNC (0x20) 142 #define GPIO_PAR_PSC3_RTS3_RTS (0x30) 143 #define GPIO_PAR_PSC3_CTS2_CANRX (0x40) 144 145 /* Bit definitions and macros for GPIO_PAR_PSC2 */ 146 #define GPIO_PAR_PSC2_TXD2 (0x04) 147 #define GPIO_PAR_PSC2_RXD2 (0x08) 148 #define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4) 149 #define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6) 150 #define GPIO_PAR_PSC2_CTS2_GPIO (0x00) 151 #define GPIO_PAR_PSC2_CTS2_BCLK (0x80) 152 #define GPIO_PAR_PSC2_CTS2_CTS (0xC0) 153 #define GPIO_PAR_PSC2_RTS2_GPIO (0x00) 154 #define GPIO_PAR_PSC2_RTS2_CANTX (0x10) 155 #define GPIO_PAR_PSC2_RTS2_FSYNC (0x20) 156 #define GPIO_PAR_PSC2_RTS2_RTS (0x30) 157 158 /* Bit definitions and macros for GPIO_PAR_PSC1 */ 159 #define GPIO_PAR_PSC1_TXD1 (0x04) 160 #define GPIO_PAR_PSC1_RXD1 (0x08) 161 #define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4) 162 #define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6) 163 #define GPIO_PAR_PSC1_CTS1_GPIO (0x00) 164 #define GPIO_PAR_PSC1_CTS1_BCLK (0x80) 165 #define GPIO_PAR_PSC1_CTS1_CTS (0xC0) 166 #define GPIO_PAR_PSC1_RTS1_GPIO (0x00) 167 #define GPIO_PAR_PSC1_RTS1_FSYNC (0x20) 168 #define GPIO_PAR_PSC1_RTS1_RTS (0x30) 169 170 /* Bit definitions and macros for GPIO_PAR_PSC0 */ 171 #define GPIO_PAR_PSC0_TXD0 (0x04) 172 #define GPIO_PAR_PSC0_RXD0 (0x08) 173 #define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4) 174 #define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6) 175 #define GPIO_PAR_PSC0_CTS0_GPIO (0x00) 176 #define GPIO_PAR_PSC0_CTS0_BCLK (0x80) 177 #define GPIO_PAR_PSC0_CTS0_CTS (0xC0) 178 #define GPIO_PAR_PSC0_RTS0_GPIO (0x00) 179 #define GPIO_PAR_PSC0_RTS0_FSYNC (0x20) 180 #define GPIO_PAR_PSC0_RTS0_RTS (0x30) 181 182 /* Bit definitions and macros for GPIO_PAR_DSPI */ 183 #define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0) 184 #define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2) 185 #define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4) 186 #define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6) 187 #define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8) 188 #define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10) 189 #define GPIO_PAR_DSPI_CS5 (0x1000) 190 #define GPIO_PAR_DSPI_CS3_GPIO (0x0000) 191 #define GPIO_PAR_DSPI_CS3_CANTX (0x0400) 192 #define GPIO_PAR_DSPI_CS3_TOUT (0x0800) 193 #define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00) 194 #define GPIO_PAR_DSPI_CS2_GPIO (0x0000) 195 #define GPIO_PAR_DSPI_CS2_CANTX (0x0100) 196 #define GPIO_PAR_DSPI_CS2_TOUT (0x0200) 197 #define GPIO_PAR_DSPI_CS2_DSPICS (0x0300) 198 #define GPIO_PAR_DSPI_CS0_GPIO (0x0000) 199 #define GPIO_PAR_DSPI_CS0_FSYNC (0x0040) 200 #define GPIO_PAR_DSPI_CS0_RTS (0x0080) 201 #define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0) 202 #define GPIO_PAR_DSPI_SCK_GPIO (0x0000) 203 #define GPIO_PAR_DSPI_SCK_BCLK (0x0010) 204 #define GPIO_PAR_DSPI_SCK_CTS (0x0020) 205 #define GPIO_PAR_DSPI_SCK_SCK (0x0030) 206 #define GPIO_PAR_DSPI_SIN_GPIO (0x0000) 207 #define GPIO_PAR_DSPI_SIN_RXD (0x0008) 208 #define GPIO_PAR_DSPI_SIN_SIN (0x000C) 209 #define GPIO_PAR_DSPI_SOUT_GPIO (0x0000) 210 #define GPIO_PAR_DSPI_SOUT_TXD (0x0002) 211 #define GPIO_PAR_DSPI_SOUT_SOUT (0x0003) 212 213 /* Bit definitions and macros for GPIO_PAR_TIMER */ 214 #define GPIO_PAR_TIMER_TOUT2 (0x01) 215 #define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1) 216 #define GPIO_PAR_TIMER_TOUT3 (0x08) 217 #define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4) 218 #define GPIO_PAR_TIMER_TIN3_CANRX (0x00) 219 #define GPIO_PAR_TIMER_TIN3_IRQ (0x20) 220 #define GPIO_PAR_TIMER_TIN3_TIN (0x30) 221 #define GPIO_PAR_TIMER_TIN2_CANRX (0x00) 222 #define GPIO_PAR_TIMER_TIN2_IRQ (0x04) 223 #define GPIO_PAR_TIMER_TIN2_TIN (0x06) 224 225 /********************************************************************* 226 * Slice Timer (SLT) 227 *********************************************************************/ 228 #define SLT_CR_RUN (0x04000000) 229 #define SLT_CR_IEN (0x02000000) 230 #define SLT_CR_TEN (0x01000000) 231 232 #define SLT_SR_BE (0x02000000) 233 #define SLT_SR_ST (0x01000000) 234 235 /********************************************************************* 236 * Interrupt Controller (INTC) 237 *********************************************************************/ 238 #define INT0_LO_RSVD0 (0) 239 #define INT0_LO_EPORT1 (1) 240 #define INT0_LO_EPORT2 (2) 241 #define INT0_LO_EPORT3 (3) 242 #define INT0_LO_EPORT4 (4) 243 #define INT0_LO_EPORT5 (5) 244 #define INT0_LO_EPORT6 (6) 245 #define INT0_LO_EPORT7 (7) 246 #define INT0_LO_EP0ISR (15) 247 #define INT0_LO_EP1ISR (16) 248 #define INT0_LO_EP2ISR (17) 249 #define INT0_LO_EP3ISR (18) 250 #define INT0_LO_EP4ISR (19) 251 #define INT0_LO_EP5ISR (20) 252 #define INT0_LO_EP6ISR (21) 253 #define INT0_LO_USBISR (22) 254 #define INT0_LO_USBAISR (23) 255 #define INT0_LO_USB (24) 256 #define INT1_LO_DSPI_RFOF_TFUF (25) 257 #define INT1_LO_DSPI_RFOF (26) 258 #define INT1_LO_DSPI_RFDF (27) 259 #define INT1_LO_DSPI_TFUF (28) 260 #define INT1_LO_DSPI_TCF (29) 261 #define INT1_LO_DSPI_TFFF (30) 262 #define INT1_LO_DSPI_EOQF (31) 263 264 #define INT0_HI_UART3 (32) 265 #define INT0_HI_UART2 (33) 266 #define INT0_HI_UART1 (34) 267 #define INT0_HI_UART0 (35) 268 #define INT0_HI_COMMTIM_TC (36) 269 #define INT0_HI_SEC (37) 270 #define INT0_HI_FEC1 (38) 271 #define INT0_HI_FEC0 (39) 272 #define INT0_HI_I2C (40) 273 #define INT0_HI_PCIARB (41) 274 #define INT0_HI_CBPCI (42) 275 #define INT0_HI_XLBPCI (43) 276 #define INT0_HI_XLBARB (47) 277 #define INT0_HI_DMA (48) 278 #define INT0_HI_CAN0_ERROR (49) 279 #define INT0_HI_CAN0_BUSOFF (50) 280 #define INT0_HI_CAN0_MBOR (51) 281 #define INT0_HI_SLT1 (53) 282 #define INT0_HI_SLT0 (54) 283 #define INT0_HI_CAN1_ERROR (55) 284 #define INT0_HI_CAN1_BUSOFF (56) 285 #define INT0_HI_CAN1_MBOR (57) 286 #define INT0_HI_GPT3 (59) 287 #define INT0_HI_GPT2 (60) 288 #define INT0_HI_GPT1 (61) 289 #define INT0_HI_GPT0 (62) 290 291 /********************************************************************* 292 * General Purpose Timers (GPTMR) 293 *********************************************************************/ 294 /* Enable and Mode Select */ 295 #define GPT_OCT(x) (x & 0x3)<<4 /* Output Compare Type */ 296 #define GPT_ICT(x) (x & 0x3) /* Input Capture Type */ 297 #define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */ 298 #define GPT_CTRL_CE 0x10 /* Counter Enable */ 299 #define GPT_CTRL_STPCNT 0x04 /* Stop continous */ 300 #define GPT_CTRL_ODRAIN 0x02 /* Open Drain */ 301 #define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */ 302 #define GPT_MODE_GPIO(x) (x & 0x3)<<4 /* Gpio Mode Type */ 303 #define GPT_TMS_ICT 0x01 /* Input Capture Enable */ 304 #define GPT_TMS_OCT 0x02 /* Output Capture Enable */ 305 #define GPT_TMS_PWM 0x03 /* PWM Capture Enable */ 306 #define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */ 307 308 #define GPT_PWM_WIDTH(x) (x & 0xffff) 309 310 /* Status */ 311 #define GPT_STA_CAPTURE(x) (x & 0xffff) 312 313 #define GPT_OVFPIN_OVF(x) (x & 0x70) 314 #define GPT_OVFPIN_PIN 0x01 315 316 #define GPT_INT_TEXP 0x08 317 #define GPT_INT_PWMP 0x04 318 #define GPT_INT_COMP 0x02 319 #define GPT_INT_CAPT 0x01 320 321 /********************************************************************* 322 * PCI 323 *********************************************************************/ 324 325 /* Bit definitions and macros for SCR */ 326 #define PCI_SCR_PE (0x80000000) /* Parity Error detected */ 327 #define PCI_SCR_SE (0x40000000) /* System error signalled */ 328 #define PCI_SCR_MA (0x20000000) /* Master aboart received */ 329 #define PCI_SCR_TR (0x10000000) /* Target abort received */ 330 #define PCI_SCR_TS (0x08000000) /* Target abort signalled */ 331 #define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ 332 #define PCI_SCR_DP (0x01000000) /* Master data parity err */ 333 #define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ 334 #define PCI_SCR_R (0x00400000) /* Reserved */ 335 #define PCI_SCR_66M (0x00200000) /* 66Mhz */ 336 #define PCI_SCR_C (0x00100000) /* Capabilities list */ 337 #define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ 338 #define PCI_SCR_S (0x00000100) /* SERR enable */ 339 #define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ 340 #define PCI_SCR_PER (0x00000040) /* Parity error response */ 341 #define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ 342 #define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ 343 #define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ 344 #define PCI_SCR_B (0x00000004) /* Bus master enable */ 345 #define PCI_SCR_M (0x00000002) /* Memory access control */ 346 #define PCI_SCR_IO (0x00000001) /* I/O access control */ 347 348 #define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ 349 #define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ 350 #define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ 351 #define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ 352 353 #define PCI_BAR_BAR0(x) (x & 0xFFFC0000) 354 #define PCI_BAR_BAR1(x) (x & 0xC0000000) 355 #define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ 356 #define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ 357 #define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ 358 359 #define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ 360 #define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ 361 #define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ 362 #define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ 363 364 #define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ 365 #define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ 366 #define PCI_GSCR_SE (0x10000000) /* SERR detected */ 367 #define PCI_GSCR_ER (0x08000000) /* Error response detected */ 368 #define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ 369 #define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ 370 #define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ 371 #define PCI_GSCR_PR (0x00000001) /* PCI reset */ 372 373 #define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ 374 #define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ 375 #define PCI_TCR1_P (0x00010000) /* Prefetch reads */ 376 #define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ 377 378 #define PCI_TCR1_B5E (0x00002000) /* */ 379 #define PCI_TCR1_B4E (0x00001000) /* */ 380 #define PCI_TCR1_B3E (0x00000800) /* */ 381 #define PCI_TCR1_B2E (0x00000400) /* */ 382 #define PCI_TCR1_B1E (0x00000200) /* */ 383 #define PCI_TCR1_B0E (0x00000100) /* */ 384 #define PCI_TCR1_CR (0x00000001) /* */ 385 386 #define PCI_TBATR_BAT0(x) (x & 0xFFFC0000) 387 #define PCI_TBATR_BAT1(x) (x & 0xC0000000) 388 #define PCI_TBATR_EN (0x00000001) /* Enable */ 389 390 #define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ 391 #define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ 392 #define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ 393 #define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ 394 #define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ 395 #define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ 396 #define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ 397 #define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ 398 #define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ 399 #define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ 400 #define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ 401 #define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ 402 #define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ 403 #define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ 404 #define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ 405 406 #define PCI_ICR_REE (0x04000000) /* Retry error enable */ 407 #define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ 408 #define PCI_ICR_TAE (0x01000000) /* Target abort enable */ 409 #define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF) 410 411 #define PCIARB_ACR_DS (0x80000000) 412 #define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17) 413 #define PCIARB_ARC_INTMINTEN (0x00010000) 414 #define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1) 415 #define PCIARB_ARC_INTMPRI (0x00000001) 416 417 #endif /* mcf547x_8x_h */ 418
