1 menu "MIPS architecture" 2 depends on MIPS 3 4 config SYS_ARCH 5 default "mips" 6 7 config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11 choice 12 prompt "Target select" 13 optional 14 15 config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select ROM_EXCEPTION_VECTORS 24 25 config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_L2_CACHE 32 select OF_CONTROL 33 select OF_ISA_BUS 34 select SUPPORTS_BIG_ENDIAN 35 select SUPPORTS_LITTLE_ENDIAN 36 select SUPPORTS_CPU_MIPS32_R1 37 select SUPPORTS_CPU_MIPS32_R2 38 select SUPPORTS_CPU_MIPS32_R6 39 select SUPPORTS_CPU_MIPS64_R1 40 select SUPPORTS_CPU_MIPS64_R2 41 select SUPPORTS_CPU_MIPS64_R6 42 select SWAP_IO_SPACE 43 select MIPS_L1_CACHE_SHIFT_6 44 select ROM_EXCEPTION_VECTORS 45 46 config TARGET_VCT 47 bool "Support vct" 48 select SUPPORTS_BIG_ENDIAN 49 select SUPPORTS_CPU_MIPS32_R1 50 select SUPPORTS_CPU_MIPS32_R2 51 select SYS_MIPS_CACHE_INIT_RAM_LOAD 52 select ROM_EXCEPTION_VECTORS 53 54 config TARGET_DBAU1X00 55 bool "Support dbau1x00" 56 select SUPPORTS_BIG_ENDIAN 57 select SUPPORTS_LITTLE_ENDIAN 58 select SUPPORTS_CPU_MIPS32_R1 59 select SUPPORTS_CPU_MIPS32_R2 60 select SYS_MIPS_CACHE_INIT_RAM_LOAD 61 select ROM_EXCEPTION_VECTORS 62 select MIPS_TUNE_4KC 63 64 config TARGET_PB1X00 65 bool "Support pb1x00" 66 select SUPPORTS_LITTLE_ENDIAN 67 select SUPPORTS_CPU_MIPS32_R1 68 select SUPPORTS_CPU_MIPS32_R2 69 select SYS_MIPS_CACHE_INIT_RAM_LOAD 70 select ROM_EXCEPTION_VECTORS 71 select MIPS_TUNE_4KC 72 73 config ARCH_ATH79 74 bool "Support QCA/Atheros ath79" 75 select OF_CONTROL 76 select DM 77 78 config ARCH_BMIPS 79 bool "Support BMIPS SoCs" 80 select OF_CONTROL 81 select DM 82 select CLK 83 select CPU 84 select RAM 85 select SYSRESET 86 87 config MACH_PIC32 88 bool "Support Microchip PIC32" 89 select OF_CONTROL 90 select DM 91 92 config TARGET_BOSTON 93 bool "Support Boston" 94 select DM 95 select DM_SERIAL 96 select OF_CONTROL 97 select MIPS_CM 98 select MIPS_L1_CACHE_SHIFT_6 99 select MIPS_L2_CACHE 100 select OF_BOARD_SETUP 101 select SUPPORTS_BIG_ENDIAN 102 select SUPPORTS_LITTLE_ENDIAN 103 select SUPPORTS_CPU_MIPS32_R1 104 select SUPPORTS_CPU_MIPS32_R2 105 select SUPPORTS_CPU_MIPS32_R6 106 select SUPPORTS_CPU_MIPS64_R1 107 select SUPPORTS_CPU_MIPS64_R2 108 select SUPPORTS_CPU_MIPS64_R6 109 select ROM_EXCEPTION_VECTORS 110 111 config TARGET_XILFPGA 112 bool "Support Imagination Xilfpga" 113 select OF_CONTROL 114 select DM 115 select DM_SERIAL 116 select DM_GPIO 117 select DM_ETH 118 select SUPPORTS_LITTLE_ENDIAN 119 select SUPPORTS_CPU_MIPS32_R1 120 select SUPPORTS_CPU_MIPS32_R2 121 select MIPS_L1_CACHE_SHIFT_4 122 select ROM_EXCEPTION_VECTORS 123 help 124 This supports IMGTEC MIPSfpga platform 125 126 endchoice 127 128 source "board/dbau1x00/Kconfig" 129 source "board/imgtec/boston/Kconfig" 130 source "board/imgtec/malta/Kconfig" 131 source "board/imgtec/xilfpga/Kconfig" 132 source "board/micronas/vct/Kconfig" 133 source "board/pb1x00/Kconfig" 134 source "board/qemu-mips/Kconfig" 135 source "arch/mips/mach-ath79/Kconfig" 136 source "arch/mips/mach-bmips/Kconfig" 137 source "arch/mips/mach-pic32/Kconfig" 138 139 if MIPS 140 141 choice 142 prompt "Endianness selection" 143 help 144 Some MIPS boards can be configured for either little or big endian 145 byte order. These modes require different U-Boot images. In general there 146 is one preferred byteorder for a particular system but some systems are 147 just as commonly used in the one or the other endianness. 148 149 config SYS_BIG_ENDIAN 150 bool "Big endian" 151 depends on SUPPORTS_BIG_ENDIAN 152 153 config SYS_LITTLE_ENDIAN 154 bool "Little endian" 155 depends on SUPPORTS_LITTLE_ENDIAN 156 157 endchoice 158 159 choice 160 prompt "CPU selection" 161 default CPU_MIPS32_R2 162 163 config CPU_MIPS32_R1 164 bool "MIPS32 Release 1" 165 depends on SUPPORTS_CPU_MIPS32_R1 166 select 32BIT 167 help 168 Choose this option to build an U-Boot for release 1 through 5 of the 169 MIPS32 architecture. 170 171 config CPU_MIPS32_R2 172 bool "MIPS32 Release 2" 173 depends on SUPPORTS_CPU_MIPS32_R2 174 select 32BIT 175 help 176 Choose this option to build an U-Boot for release 2 through 5 of the 177 MIPS32 architecture. 178 179 config CPU_MIPS32_R6 180 bool "MIPS32 Release 6" 181 depends on SUPPORTS_CPU_MIPS32_R6 182 select 32BIT 183 help 184 Choose this option to build an U-Boot for release 6 or later of the 185 MIPS32 architecture. 186 187 config CPU_MIPS64_R1 188 bool "MIPS64 Release 1" 189 depends on SUPPORTS_CPU_MIPS64_R1 190 select 64BIT 191 help 192 Choose this option to build a kernel for release 1 through 5 of the 193 MIPS64 architecture. 194 195 config CPU_MIPS64_R2 196 bool "MIPS64 Release 2" 197 depends on SUPPORTS_CPU_MIPS64_R2 198 select 64BIT 199 help 200 Choose this option to build a kernel for release 2 through 5 of the 201 MIPS64 architecture. 202 203 config CPU_MIPS64_R6 204 bool "MIPS64 Release 6" 205 depends on SUPPORTS_CPU_MIPS64_R6 206 select 64BIT 207 help 208 Choose this option to build a kernel for release 6 or later of the 209 MIPS64 architecture. 210 211 endchoice 212 213 menu "General setup" 214 215 config ROM_EXCEPTION_VECTORS 216 bool "Build U-Boot image with exception vectors" 217 help 218 Enable this to include exception vectors in the U-Boot image. This is 219 required if the U-Boot entry point is equal to the address of the 220 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 221 U-Boot booted from parallel NOR flash). 222 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 223 In that case the image size will be reduced by 0x500 bytes. 224 225 config MIPS_CM_BASE 226 hex "MIPS CM GCR Base Address" 227 depends on MIPS_CM 228 default 0x16100000 if TARGET_BOSTON 229 default 0x1fbf8000 230 help 231 The physical base address at which to map the MIPS Coherence Manager 232 Global Configuration Registers (GCRs). This should be set such that 233 the GCRs occupy a region of the physical address space which is 234 otherwise unused, or at minimum that software doesn't need to access. 235 236 endmenu 237 238 menu "OS boot interface" 239 240 config MIPS_BOOT_CMDLINE_LEGACY 241 bool "Hand over legacy command line to Linux kernel" 242 default y 243 help 244 Enable this option if you want U-Boot to hand over the Yamon-style 245 command line to the kernel. All bootargs will be prepared as argc/argv 246 compatible list. The argument count (argc) is stored in register $a0. 247 The address of the argument list (argv) is stored in register $a1. 248 249 config MIPS_BOOT_ENV_LEGACY 250 bool "Hand over legacy environment to Linux kernel" 251 default y 252 help 253 Enable this option if you want U-Boot to hand over the Yamon-style 254 environment to the kernel. Information like memory size, initrd 255 address and size will be prepared as zero-terminated key/value list. 256 The address of the environment is stored in register $a2. 257 258 config MIPS_BOOT_FDT 259 bool "Hand over a flattened device tree to Linux kernel" 260 default n 261 help 262 Enable this option if you want U-Boot to hand over a flattened 263 device tree to the kernel. According to UHI register $a0 will be set 264 to -2 and the FDT address is stored in $a1. 265 266 endmenu 267 268 config SUPPORTS_BIG_ENDIAN 269 bool 270 271 config SUPPORTS_LITTLE_ENDIAN 272 bool 273 274 config SUPPORTS_CPU_MIPS32_R1 275 bool 276 277 config SUPPORTS_CPU_MIPS32_R2 278 bool 279 280 config SUPPORTS_CPU_MIPS32_R6 281 bool 282 283 config SUPPORTS_CPU_MIPS64_R1 284 bool 285 286 config SUPPORTS_CPU_MIPS64_R2 287 bool 288 289 config SUPPORTS_CPU_MIPS64_R6 290 bool 291 292 config CPU_MIPS32 293 bool 294 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 295 296 config CPU_MIPS64 297 bool 298 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 299 300 config MIPS_TUNE_4KC 301 bool 302 303 config MIPS_TUNE_14KC 304 bool 305 306 config MIPS_TUNE_24KC 307 bool 308 309 config MIPS_TUNE_34KC 310 bool 311 312 config MIPS_TUNE_74KC 313 bool 314 315 config 32BIT 316 bool 317 318 config 64BIT 319 bool 320 321 config SWAP_IO_SPACE 322 bool 323 324 config SYS_MIPS_CACHE_INIT_RAM_LOAD 325 bool 326 327 config MIPS_INIT_STACK_IN_SRAM 328 bool 329 default n 330 help 331 Select this if the initial stack frame could be setup in SRAM. 332 Normally the initial stack frame is set up in DRAM which is often 333 only available after lowlevel_init. With this option the initial 334 stack frame and the early C environment is set up before 335 lowlevel_init. Thus lowlevel_init does not need to be implemented 336 in assembler. 337 338 config SYS_DCACHE_SIZE 339 int 340 default 0 341 help 342 The total size of the L1 Dcache, if known at compile time. 343 344 config SYS_DCACHE_LINE_SIZE 345 int 346 default 0 347 help 348 The size of L1 Dcache lines, if known at compile time. 349 350 config SYS_ICACHE_SIZE 351 int 352 default 0 353 help 354 The total size of the L1 ICache, if known at compile time. 355 356 config SYS_ICACHE_LINE_SIZE 357 int 358 default 0 359 help 360 The size of L1 Icache lines, if known at compile time. 361 362 config SYS_CACHE_SIZE_AUTO 363 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 364 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 365 help 366 Select this (or let it be auto-selected by not defining any cache 367 sizes) in order to allow U-Boot to automatically detect the sizes 368 of caches at runtime. This has a small cost in code size & runtime 369 so if you know the cache configuration for your system at compile 370 time it would be beneficial to configure it. 371 372 config MIPS_L1_CACHE_SHIFT_4 373 bool 374 375 config MIPS_L1_CACHE_SHIFT_5 376 bool 377 378 config MIPS_L1_CACHE_SHIFT_6 379 bool 380 381 config MIPS_L1_CACHE_SHIFT_7 382 bool 383 384 config MIPS_L1_CACHE_SHIFT 385 int 386 default "7" if MIPS_L1_CACHE_SHIFT_7 387 default "6" if MIPS_L1_CACHE_SHIFT_6 388 default "5" if MIPS_L1_CACHE_SHIFT_5 389 default "4" if MIPS_L1_CACHE_SHIFT_4 390 default "5" 391 392 config MIPS_L2_CACHE 393 bool 394 help 395 Select this if your system includes an L2 cache and you want U-Boot 396 to initialise & maintain it. 397 398 config DYNAMIC_IO_PORT_BASE 399 bool 400 401 config MIPS_CM 402 bool 403 help 404 Select this if your system contains a MIPS Coherence Manager and you 405 wish U-Boot to configure it or make use of it to retrieve system 406 information such as cache configuration. 407 408 endif 409 410 endmenu 411
