1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 lvaro Fernndez Rojas <noltari (a] gmail.com> 4 */ 5 6 #include <dt-bindings/clock/bcm63268-clock.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/power-domain/bcm63268-power-domain.h> 9 #include <dt-bindings/reset/bcm63268-reset.h> 10 #include "skeleton.dtsi" 11 12 / { 13 compatible = "brcm,bcm63268"; 14 15 aliases { 16 spi0 = &lsspi; 17 spi1 = &hsspi; 18 }; 19 20 cpus { 21 reg = <0x10000000 0x4>; 22 #address-cells = <1>; 23 #size-cells = <0>; 24 u-boot,dm-pre-reloc; 25 26 cpu@0 { 27 compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; 28 device_type = "cpu"; 29 reg = <0>; 30 u-boot,dm-pre-reloc; 31 }; 32 33 cpu@1 { 34 compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; 35 device_type = "cpu"; 36 reg = <1>; 37 u-boot,dm-pre-reloc; 38 }; 39 }; 40 41 clocks { 42 compatible = "simple-bus"; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 u-boot,dm-pre-reloc; 46 47 hsspi_pll: hsspi-pll { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <400000000>; 51 }; 52 53 periph_osc: periph-osc { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <50000000>; 57 u-boot,dm-pre-reloc; 58 }; 59 60 periph_clk: periph-clk { 61 compatible = "brcm,bcm6345-clk"; 62 reg = <0x10000004 0x4>; 63 #clock-cells = <1>; 64 }; 65 66 timer_clk: timer-clk { 67 compatible = "brcm,bcm6345-clk"; 68 reg = <0x100000ac 0x4>; 69 #clock-cells = <1>; 70 }; 71 }; 72 73 ubus { 74 compatible = "simple-bus"; 75 #address-cells = <1>; 76 #size-cells = <1>; 77 u-boot,dm-pre-reloc; 78 79 pll_cntl: syscon@10000008 { 80 compatible = "syscon"; 81 reg = <0x10000008 0x4>; 82 }; 83 84 syscon-reboot { 85 compatible = "syscon-reboot"; 86 regmap = <&pll_cntl>; 87 offset = <0x0>; 88 mask = <0x1>; 89 }; 90 91 periph_rst: reset-controller@10000010 { 92 compatible = "brcm,bcm6345-reset"; 93 reg = <0x10000010 0x4>; 94 #reset-cells = <1>; 95 }; 96 97 wdt: watchdog@1000009c { 98 compatible = "brcm,bcm6345-wdt"; 99 reg = <0x1000009c 0xc>; 100 clocks = <&periph_osc>; 101 }; 102 103 wdt-reboot { 104 compatible = "wdt-reboot"; 105 wdt = <&wdt>; 106 }; 107 108 gpio1: gpio-controller@100000c0 { 109 compatible = "brcm,bcm6345-gpio"; 110 reg = <0x100000c0 0x4>, <0x100000c8 0x4>; 111 gpio-controller; 112 #gpio-cells = <2>; 113 ngpios = <20>; 114 115 status = "disabled"; 116 }; 117 118 gpio0: gpio-controller@100000c4 { 119 compatible = "brcm,bcm6345-gpio"; 120 reg = <0x100000c4 0x4>, <0x100000cc 0x4>; 121 gpio-controller; 122 #gpio-cells = <2>; 123 124 status = "disabled"; 125 }; 126 127 uart0: serial@10000180 { 128 compatible = "brcm,bcm6345-uart"; 129 reg = <0x10000180 0x18>; 130 clocks = <&periph_osc>; 131 132 status = "disabled"; 133 }; 134 135 uart1: serial@100001a0 { 136 compatible = "brcm,bcm6345-uart"; 137 reg = <0x100001a0 0x18>; 138 clocks = <&periph_osc>; 139 140 status = "disabled"; 141 }; 142 143 periph_pwr: power-controller@1000184c { 144 compatible = "brcm,bcm6328-power-domain"; 145 reg = <0x1000184c 0x4>; 146 #power-domain-cells = <1>; 147 }; 148 149 lsspi: spi@10000800 { 150 compatible = "brcm,bcm6358-spi"; 151 reg = <0x10000800 0x70c>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 clocks = <&periph_clk BCM63268_CLK_SPI>; 155 resets = <&periph_rst BCM63268_RST_SPI>; 156 spi-max-frequency = <20000000>; 157 num-cs = <8>; 158 159 status = "disabled"; 160 }; 161 162 hsspi: spi@10001000 { 163 compatible = "brcm,bcm6328-hsspi"; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 reg = <0x10001000 0x600>; 167 clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>; 168 clock-names = "hsspi", "pll"; 169 resets = <&periph_rst BCM63268_RST_SPI>; 170 spi-max-frequency = <50000000>; 171 num-cs = <8>; 172 173 status = "disabled"; 174 }; 175 176 leds: led-controller@10001900 { 177 compatible = "brcm,bcm6328-leds"; 178 reg = <0x10001900 0x24>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 status = "disabled"; 183 }; 184 185 ehci: usb-controller@10002500 { 186 compatible = "brcm,bcm63268-ehci", "generic-ehci"; 187 reg = <0x10002500 0x100>; 188 phys = <&usbh>; 189 big-endian; 190 191 status = "disabled"; 192 }; 193 194 ohci: usb-controller@10002600 { 195 compatible = "brcm,bcm63268-ohci", "generic-ohci"; 196 reg = <0x10002600 0x100>; 197 phys = <&usbh>; 198 big-endian; 199 200 status = "disabled"; 201 }; 202 203 usbh: usb-phy@10002700 { 204 compatible = "brcm,bcm63268-usbh"; 205 reg = <0x10002700 0x38>; 206 #phy-cells = <0>; 207 clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>; 208 clock-names = "usbh", "usb_ref"; 209 power-domains = <&periph_pwr BCM63268_PWR_USBH>; 210 resets = <&periph_rst BCM63268_RST_USBH>; 211 212 status = "disabled"; 213 }; 214 215 memory-controller@10003000 { 216 compatible = "brcm,bcm6328-mc"; 217 reg = <0x10003000 0x894>; 218 u-boot,dm-pre-reloc; 219 }; 220 }; 221 }; 222
