1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 lvaro Fernndez Rojas <noltari (a] gmail.com> 4 */ 5 6 #include <dt-bindings/clock/bcm6328-clock.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/power-domain/bcm6328-power-domain.h> 9 #include <dt-bindings/reset/bcm6328-reset.h> 10 #include "skeleton.dtsi" 11 12 / { 13 compatible = "brcm,bcm6328"; 14 15 aliases { 16 spi0 = &spi; 17 }; 18 19 cpus { 20 reg = <0x10000000 0x4>; 21 #address-cells = <1>; 22 #size-cells = <0>; 23 u-boot,dm-pre-reloc; 24 25 cpu@0 { 26 compatible = "brcm,bcm6328-cpu", "mips,mips4Kc"; 27 device_type = "cpu"; 28 reg = <0>; 29 u-boot,dm-pre-reloc; 30 }; 31 32 cpu@1 { 33 compatible = "brcm,bcm6328-cpu", "mips,mips4Kc"; 34 device_type = "cpu"; 35 reg = <1>; 36 u-boot,dm-pre-reloc; 37 }; 38 }; 39 40 clocks { 41 compatible = "simple-bus"; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 u-boot,dm-pre-reloc; 45 46 hsspi_pll: hsspi-pll { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <133333333>; 50 }; 51 52 periph_osc: periph-osc { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <50000000>; 56 u-boot,dm-pre-reloc; 57 }; 58 59 periph_clk: periph-clk { 60 compatible = "brcm,bcm6345-clk"; 61 reg = <0x10000004 0x4>; 62 #clock-cells = <1>; 63 }; 64 }; 65 66 ubus { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 u-boot,dm-pre-reloc; 71 72 periph_rst: reset-controller@10000010 { 73 compatible = "brcm,bcm6345-reset"; 74 reg = <0x10000010 0x4>; 75 #reset-cells = <1>; 76 }; 77 78 pll_cntl: syscon@10000068 { 79 compatible = "syscon"; 80 reg = <0x10000068 0x4>; 81 }; 82 83 syscon-reboot { 84 compatible = "syscon-reboot"; 85 regmap = <&pll_cntl>; 86 offset = <0x0>; 87 mask = <0x1>; 88 }; 89 90 wdt: watchdog@1000005c { 91 compatible = "brcm,bcm6345-wdt"; 92 reg = <0x1000005c 0xc>; 93 clocks = <&periph_osc>; 94 }; 95 96 wdt-reboot { 97 compatible = "wdt-reboot"; 98 wdt = <&wdt>; 99 }; 100 101 gpio: gpio-controller@10000084 { 102 compatible = "brcm,bcm6345-gpio"; 103 reg = <0x10000084 0x4>, <0x1000008c 0x4>; 104 gpio-controller; 105 #gpio-cells = <2>; 106 107 status = "disabled"; 108 }; 109 110 uart0: serial@10000100 { 111 compatible = "brcm,bcm6345-uart"; 112 reg = <0x10000100 0x18>; 113 clocks = <&periph_osc>; 114 115 status = "disabled"; 116 }; 117 118 uart1: serial@10000120 { 119 compatible = "brcm,bcm6345-uart"; 120 reg = <0x10000120 0x18>; 121 clocks = <&periph_osc>; 122 123 status = "disabled"; 124 }; 125 126 leds: led-controller@10000800 { 127 compatible = "brcm,bcm6328-leds"; 128 reg = <0x10000800 0x24>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 132 status = "disabled"; 133 }; 134 135 spi: spi@10001000 { 136 compatible = "brcm,bcm6328-hsspi"; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 reg = <0x10001000 0x600>; 140 clocks = <&periph_clk BCM6328_CLK_HSSPI>, <&hsspi_pll>; 141 clock-names = "hsspi", "pll"; 142 resets = <&periph_rst BCM6328_RST_SPI>; 143 spi-max-frequency = <33333334>; 144 num-cs = <3>; 145 146 status = "disabled"; 147 }; 148 149 periph_pwr: power-controller@10001848 { 150 compatible = "brcm,bcm6328-power-domain"; 151 reg = <0x10001848 0x4>; 152 #power-domain-cells = <1>; 153 }; 154 155 ehci: usb-controller@10002500 { 156 compatible = "brcm,bcm6328-ehci", "generic-ehci"; 157 reg = <0x10002500 0x100>; 158 phys = <&usbh>; 159 big-endian; 160 161 status = "disabled"; 162 }; 163 164 ohci: usb-controller@10002600 { 165 compatible = "brcm,bcm6328-ohci", "generic-ohci"; 166 reg = <0x10002600 0x100>; 167 phys = <&usbh>; 168 big-endian; 169 170 status = "disabled"; 171 }; 172 173 usbh: usb-phy@10002700 { 174 compatible = "brcm,bcm6328-usbh"; 175 reg = <0x10002700 0x38>; 176 #phy-cells = <0>; 177 clocks = <&periph_clk BCM6328_CLK_USBH>; 178 clock-names = "usbh"; 179 power-domains = <&periph_pwr BCM6328_PWR_USBH>; 180 resets = <&periph_rst BCM6328_RST_USBH>; 181 182 status = "disabled"; 183 }; 184 185 memory-controller@10003000 { 186 compatible = "brcm,bcm6328-mc"; 187 reg = <0x10003000 0x864>; 188 u-boot,dm-pre-reloc; 189 }; 190 }; 191 }; 192
