1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Cache operations for the cache instruction. 4 * 5 * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle 6 * (C) Copyright 1999 Silicon Graphics, Inc. 7 */ 8 #ifndef __ASM_CACHEOPS_H 9 #define __ASM_CACHEOPS_H 10 11 #ifndef __ASSEMBLY__ 12 13 static inline void mips_cache(int op, const volatile void *addr) 14 { 15 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE 16 __builtin_mips_cache(op, addr); 17 #else 18 __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr)); 19 #endif 20 } 21 22 #endif /* !__ASSEMBLY__ */ 23 24 /* 25 * Cache Operations available on all MIPS processors with R4000-style caches 26 */ 27 #define INDEX_INVALIDATE_I 0x00 28 #define INDEX_WRITEBACK_INV_D 0x01 29 #define INDEX_LOAD_TAG_I 0x04 30 #define INDEX_LOAD_TAG_D 0x05 31 #define INDEX_STORE_TAG_I 0x08 32 #define INDEX_STORE_TAG_D 0x09 33 #if defined(CONFIG_CPU_LOONGSON2) 34 #define HIT_INVALIDATE_I 0x00 35 #else 36 #define HIT_INVALIDATE_I 0x10 37 #endif 38 #define HIT_INVALIDATE_D 0x11 39 #define HIT_WRITEBACK_INV_D 0x15 40 41 /* 42 * R4000-specific cacheops 43 */ 44 #define CREATE_DIRTY_EXCL_D 0x0d 45 #define FILL 0x14 46 #define HIT_WRITEBACK_I 0x18 47 #define HIT_WRITEBACK_D 0x19 48 49 /* 50 * R4000SC and R4400SC-specific cacheops 51 */ 52 #define INDEX_INVALIDATE_SI 0x02 53 #define INDEX_WRITEBACK_INV_SD 0x03 54 #define INDEX_LOAD_TAG_SI 0x06 55 #define INDEX_LOAD_TAG_SD 0x07 56 #define INDEX_STORE_TAG_SI 0x0A 57 #define INDEX_STORE_TAG_SD 0x0B 58 #define CREATE_DIRTY_EXCL_SD 0x0f 59 #define HIT_INVALIDATE_SI 0x12 60 #define HIT_INVALIDATE_SD 0x13 61 #define HIT_WRITEBACK_INV_SD 0x17 62 #define HIT_WRITEBACK_SD 0x1b 63 #define HIT_SET_VIRTUAL_SI 0x1e 64 #define HIT_SET_VIRTUAL_SD 0x1f 65 66 /* 67 * R5000-specific cacheops 68 */ 69 #define R5K_PAGE_INVALIDATE_S 0x17 70 71 /* 72 * RM7000-specific cacheops 73 */ 74 #define PAGE_INVALIDATE_T 0x16 75 76 /* 77 * R10000-specific cacheops 78 * 79 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 80 * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 81 */ 82 #define INDEX_WRITEBACK_INV_S 0x03 83 #define INDEX_LOAD_TAG_S 0x07 84 #define INDEX_STORE_TAG_S 0x0B 85 #define HIT_INVALIDATE_S 0x13 86 #define CACHE_BARRIER 0x14 87 #define HIT_WRITEBACK_INV_S 0x17 88 #define INDEX_LOAD_DATA_I 0x18 89 #define INDEX_LOAD_DATA_D 0x19 90 #define INDEX_LOAD_DATA_S 0x1b 91 #define INDEX_STORE_DATA_I 0x1c 92 #define INDEX_STORE_DATA_D 0x1d 93 #define INDEX_STORE_DATA_S 0x1f 94 95 #endif /* __ASM_CACHEOPS_H */ 96
