1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2000-2002 4 * Wolfgang Denk, DENX Software Engineering, wd (at) denx.de. 5 * 6 * (C) Copyright 2002 (440 port) 7 * Scott McNutt, Artesyn Communication Producs, smcnutt (at) artsyncp.com 8 * 9 * (C) Copyright 2003 Motorola Inc. (MPC85xx port) 10 * Xianghua Xiao (X.Xiao (at) motorola.com) 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <command.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 #ifdef CONFIG_POST 19 #include <post.h> 20 #endif 21 22 void interrupt_init_cpu(unsigned *decrementer_count) 23 { 24 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; 25 26 #ifdef CONFIG_POST 27 /* 28 * The POST word is stored in the PIC's TFRR register which gets 29 * cleared when the PIC is reset. Save it off so we can restore it 30 * later. 31 */ 32 ulong post_word = post_word_load(); 33 #endif 34 35 out_be32(&pic->gcr, MPC85xx_PICGCR_RST); 36 while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) 37 ; 38 out_be32(&pic->gcr, MPC85xx_PICGCR_M); 39 in_be32(&pic->gcr); 40 41 *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; 42 43 /* PIE is same as DIE, dec interrupt enable */ 44 mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE); 45 46 #ifdef CONFIG_INTERRUPTS 47 pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ 48 debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1); 49 50 pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ 51 debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2); 52 53 pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ 54 debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3); 55 56 #ifdef CONFIG_PCI1 57 pic->iivpr8 = 0x810008; /* enable pci1 interrupts */ 58 debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8); 59 #endif 60 #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) 61 pic->iivpr9 = 0x810009; /* enable pci1 interrupts */ 62 debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9); 63 #endif 64 #ifdef CONFIG_PCIE1 65 pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */ 66 debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10); 67 #endif 68 #ifdef CONFIG_PCIE3 69 pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */ 70 debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11); 71 #endif 72 73 pic->ctpr=0; /* 40080 clear current task priority register */ 74 #endif 75 76 #ifdef CONFIG_POST 77 post_word_store(post_word); 78 #endif 79 } 80 81 /* Install and free a interrupt handler. Not implemented yet. */ 82 83 void 84 irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) 85 { 86 return; 87 } 88 89 void 90 irq_free_handler(int vec) 91 { 92 return; 93 } 94 95 void timer_interrupt_cpu(struct pt_regs *regs) 96 { 97 /* PIS is same as DIS, dec interrupt status */ 98 mtspr(SPRN_TSR, TSR_PIS); 99 } 100 101 #if defined(CONFIG_CMD_IRQ) 102 /* irqinfo - print information about PCI devices,not implemented. */ 103 int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 104 { 105 return 0; 106 } 107 #endif 108
