1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * 5 * Shengzhou Liu <Shengzhou.Liu (at) freescale.com> 6 */ 7 8 #include <common.h> 9 #include <asm/fsl_serdes.h> 10 #include <asm/processor.h> 11 #include "fsl_corenet2_serdes.h" 12 13 struct serdes_config { 14 u32 protocol; 15 u8 lanes[SRDS_MAX_LANES]; 16 }; 17 18 static const struct serdes_config serdes1_cfg_tbl[] = { 19 /* SerDes 1 */ 20 {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10, 21 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 22 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 23 {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1, 24 SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} }, 25 {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 26 SGMII_FM1_DTSEC2, PCIE4, PCIE4, 27 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 28 {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 29 SGMII_FM1_DTSEC2, PCIE4, PCIE4, 30 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 31 {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3, 32 PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 33 {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, 34 PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 35 {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 36 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 37 {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 38 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 39 {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 40 SGMII_FM1_DTSEC2, PCIE4, PCIE1, 41 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 42 {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10, 43 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 44 PCIE4, PCIE4, PCIE4, PCIE4} }, 45 {0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 46 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 47 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 48 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 49 {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 50 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 51 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 52 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 53 {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 54 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 55 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 56 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 57 {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 58 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 59 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 60 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 61 {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 62 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 63 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 64 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 65 {0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 66 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 67 PCIE4, SGMII_FM1_DTSEC4, 68 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 69 {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 70 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 71 PCIE4, SGMII_FM1_DTSEC4, 72 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 73 {0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 74 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 75 PCIE4, SGMII_FM1_DTSEC4, 76 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 77 {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 78 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 79 PCIE4, SGMII_FM1_DTSEC4, 80 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 81 {0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 82 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 83 PCIE4, SGMII_FM1_DTSEC4, 84 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 85 {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 86 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 87 PCIE4, SGMII_FM1_DTSEC4, 88 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 89 {0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10, 90 XFI_FM1_MAC1, XFI_FM1_MAC2, 91 PCIE4, SGMII_FM1_DTSEC4, 92 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 93 {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10, 94 XFI_FM1_MAC1, XFI_FM1_MAC2, 95 PCIE4, SGMII_FM1_DTSEC4, 96 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 97 {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10, 98 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 99 PCIE4, PCIE4, PCIE4, PCIE4} }, 100 {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10, 101 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 102 SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 103 {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 104 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 105 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 106 {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 107 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 108 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 109 {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 110 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 111 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 112 {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 113 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 114 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 115 {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 116 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 117 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 118 {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 119 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 120 PCIE4, PCIE4, PCIE4, PCIE4} }, 121 {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 122 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 123 PCIE4, PCIE4, PCIE4, PCIE4} }, 124 {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 125 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 126 PCIE4, PCIE4, PCIE4, PCIE4} }, 127 {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10, 128 XFI_FM1_MAC1, XFI_FM1_MAC2, 129 PCIE4, PCIE4, PCIE4, PCIE4} }, 130 {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3, 131 PCIE4, PCIE4, PCIE4, PCIE4} }, 132 {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3, 133 PCIE3, PCIE3, PCIE3, PCIE3} }, 134 {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 135 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 136 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 137 {0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 138 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 139 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 140 {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 141 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 142 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 143 {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 144 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 145 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 146 {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 147 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 148 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 149 {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10, 150 XFI_FM1_MAC1, XFI_FM1_MAC2, 151 PCIE4, PCIE4, PCIE4, PCIE4} }, 152 {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3, 153 PCIE4, PCIE4, PCIE4, PCIE4} }, 154 {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 155 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 156 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 157 {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, 158 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 159 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 160 {} 161 }; 162 163 #ifndef CONFIG_ARCH_T2081 164 static const struct serdes_config serdes2_cfg_tbl[] = { 165 /* SerDes 2 */ 166 {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, 167 {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, 168 {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, 169 {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, 170 {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, 171 {0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, 172 {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, 173 {0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} }, 174 {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, 175 {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, 176 {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, 177 {} 178 }; 179 #endif 180 181 static const struct serdes_config *serdes_cfg_tbl[] = { 182 serdes1_cfg_tbl, 183 #ifndef CONFIG_ARCH_T2081 184 serdes2_cfg_tbl, 185 #endif 186 }; 187 188 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 189 { 190 const struct serdes_config *ptr; 191 192 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 193 return 0; 194 195 ptr = serdes_cfg_tbl[serdes]; 196 while (ptr->protocol) { 197 if (ptr->protocol == cfg) 198 return ptr->lanes[lane]; 199 ptr++; 200 } 201 return 0; 202 } 203 204 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 205 { 206 int i; 207 const struct serdes_config *ptr; 208 209 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 210 return 0; 211 212 ptr = serdes_cfg_tbl[serdes]; 213 while (ptr->protocol) { 214 if (ptr->protocol == prtcl) 215 break; 216 ptr++; 217 } 218 219 if (!ptr->protocol) 220 return 0; 221 222 for (i = 0; i < SRDS_MAX_LANES; i++) { 223 if (ptr->lanes[i] != NONE) 224 return 1; 225 } 226 227 return 0; 228 } 229
