1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2009-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef _ASM_CONFIG_H_ 7 #define _ASM_CONFIG_H_ 8 9 #ifdef CONFIG_MPC85xx 10 #include <asm/config_mpc85xx.h> 11 #endif 12 13 #ifdef CONFIG_MPC86xx 14 #include <asm/config_mpc86xx.h> 15 #endif 16 17 #ifdef CONFIG_MPC83xx 18 #endif 19 20 #ifndef HWCONFIG_BUFFER_SIZE 21 #define HWCONFIG_BUFFER_SIZE 256 22 #endif 23 24 /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ 25 #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) 26 # ifndef CONFIG_HARD_SPI 27 # define CONFIG_HARD_SPI 28 # endif 29 #endif 30 31 #define CONFIG_LMB 32 #define CONFIG_SYS_BOOT_RAMDISK_HIGH 33 34 #ifndef CONFIG_MAX_MEM_MAPPED 35 #if defined(CONFIG_E500) || \ 36 defined(CONFIG_MPC86xx) || \ 37 defined(CONFIG_E300) 38 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 39 #else 40 #define CONFIG_MAX_MEM_MAPPED (256 << 20) 41 #endif 42 #endif 43 44 /* Check if boards need to enable FSL DMA engine for SDRAM init */ 45 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 46 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 47 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 48 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 49 #define CONFIG_FSL_DMA 50 #endif 51 #endif 52 53 /* 54 * Provide a default boot page translation virtual address that lines up with 55 * Freescale's default e500 reset page. 56 */ 57 #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 58 #ifndef CONFIG_BPTR_VIRT_ADDR 59 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 60 #endif 61 #endif 62 63 /* Since so many PPC SOCs have a semi-common LBC, define this here */ 64 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 65 defined(CONFIG_MPC83xx) 66 #if !defined(CONFIG_FSL_IFC) 67 #define CONFIG_FSL_LBC 68 #endif 69 #endif 70 71 /* The TSEC driver uses the PHYLIB infrastructure */ 72 #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB) 73 #include <config_phylib_all_drivers.h> 74 #endif /* TSEC_ENET */ 75 76 /* The FMAN driver uses the PHYLIB infrastructure */ 77 78 /* All PPC boards must swap IDE bytes */ 79 #define CONFIG_IDE_SWAP_IO 80 81 #if defined(CONFIG_DM_SERIAL) 82 /* 83 * TODO: Convert this to a clock driver exists that can give us the UART 84 * clock here. 85 */ 86 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 87 #endif 88 89 #endif /* _ASM_CONFIG_H_ */ 90
