1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2008 Renesas Solutions Corp. 4 * 5 * SH7723 Internal I/O register 6 */ 7 8 #ifndef _ASM_CPU_SH7723_H_ 9 #define _ASM_CPU_SH7723_H_ 10 11 #define CACHE_OC_NUM_WAYS 4 12 #define CCR_CACHE_INIT 0x0000090d 13 14 /* EXP */ 15 #define TRA 0xFF000020 16 #define EXPEVT 0xFF000024 17 #define INTEVT 0xFF000028 18 19 /* MMU */ 20 #define PTEH 0xFF000000 21 #define PTEL 0xFF000004 22 #define TTB 0xFF000008 23 #define TEA 0xFF00000C 24 #define MMUCR 0xFF000010 25 #define PASCR 0xFF000070 26 #define IRMCR 0xFF000078 27 28 /* CACHE */ 29 #define CCR 0xFF00001C 30 #define RAMCR 0xFF000074 31 32 /* INTC */ 33 34 /* BSC */ 35 #define CMNCR 0xFEC10000 36 #define CS0BCR 0xFEC10004 37 #define CS2BCR 0xFEC10008 38 #define CS4BCR 0xFEC10010 39 #define CS5ABCR 0xFEC10014 40 #define CS5BBCR 0xFEC10018 41 #define CS6ABCR 0xFEC1001C 42 #define CS6BBCR 0xFEC10020 43 #define CS0WCR 0xFEC10024 44 #define CS2WCR 0xFEC10028 45 #define CS4WCR 0xFEC10030 46 #define CS5AWCR 0xFEC10034 47 #define CS5BWCR 0xFEC10038 48 #define CS6AWCR 0xFEC1003C 49 #define CS6BWCR 0xFEC10040 50 #define RBWTCNT 0xFEC10054 51 52 /* SBSC */ 53 #define SBSC_SDCR 0xFE400008 54 #define SBSC_SDWCR 0xFE40000C 55 #define SBSC_SDPCR 0xFE400010 56 #define SBSC_RTCSR 0xFE400014 57 #define SBSC_RTCNT 0xFE400018 58 #define SBSC_RTCOR 0xFE40001C 59 #define SBSC_RFCR 0xFE400020 60 61 /* DMAC */ 62 63 /* CPG */ 64 #define FRQCR 0xA4150000 65 #define VCLKCR 0xA4150004 66 #define SCLKACR 0xA4150008 67 #define SCLKBCR 0xA415000C 68 #define IRDACLKCR 0xA4150018 69 #define PLLCR 0xA4150024 70 #define DLLFRQ 0xA4150050 71 72 /* LOW POWER MODE */ 73 #define STBCR 0xA4150020 74 #define MSTPCR0 0xA4150030 75 #define MSTPCR1 0xA4150034 76 #define MSTPCR2 0xA4150038 77 78 /* RWDT */ 79 #define RWTCNT 0xA4520000 80 #define RWTCSR 0xA4520004 81 #define WTCNT RWTCNT 82 83 /* TMU */ 84 #define TMU_BASE 0xFFD80000 85 86 /* TPU */ 87 88 /* CMT */ 89 #define CMSTR 0xA44A0000 90 #define CMCSR 0xA44A0060 91 #define CMCNT 0xA44A0064 92 #define CMCOR 0xA44A0068 93 94 /* MSIOF */ 95 96 /* SCIF */ 97 #define SCIF0_BASE 0xFFE00000 98 #define SCIF1_BASE 0xFFE10000 99 #define SCIF2_BASE 0xFFE20000 100 #define SCIF3_BASE 0xa4e30000 101 #define SCIF4_BASE 0xa4e40000 102 #define SCIF5_BASE 0xa4e50000 103 104 /* RTC */ 105 /* IrDA */ 106 /* KEYSC */ 107 /* USB */ 108 /* IIC */ 109 /* FLCTL */ 110 /* VPU */ 111 /* VIO(CEU) */ 112 /* VIO(VEU) */ 113 /* VIO(BEU) */ 114 /* 2DG */ 115 /* LCDC */ 116 /* VOU */ 117 /* TSIF */ 118 /* SIU */ 119 /* ATAPI */ 120 121 /* PFC */ 122 #define PACR 0xA4050100 123 #define PBCR 0xA4050102 124 #define PCCR 0xA4050104 125 #define PDCR 0xA4050106 126 #define PECR 0xA4050108 127 #define PFCR 0xA405010A 128 #define PGCR 0xA405010C 129 #define PHCR 0xA405010E 130 #define PJCR 0xA4050110 131 #define PKCR 0xA4050112 132 #define PLCR 0xA4050114 133 #define PMCR 0xA4050116 134 #define PNCR 0xA4050118 135 #define PQCR 0xA405011A 136 #define PRCR 0xA405011C 137 #define PSCR 0xA405011E 138 #define PTCR 0xA4050140 139 #define PUCR 0xA4050142 140 #define PVCR 0xA4050144 141 #define PWCR 0xA4050146 142 #define PXCR 0xA4050148 143 #define PYCR 0xA405014A 144 #define PZCR 0xA405014C 145 #define PSELA 0xA405014E 146 #define PSELB 0xA4050150 147 #define PSELC 0xA4050152 148 #define PSELD 0xA4050154 149 #define HIZCRA 0xA4050158 150 #define HIZCRB 0xA405015A 151 #define HIZCRC 0xA405015C 152 #define HIZCRD 0xA405015E 153 #define MSELCRA 0xA4050180 154 #define MSELCRB 0xA4050182 155 #define PULCR 0xA4050184 156 #define DRVCRA 0xA405018A 157 #define DRVCRB 0xA405018C 158 159 /* I/O Port */ 160 #define PADR 0xA4050120 161 #define PBDR 0xA4050122 162 #define PCDR 0xA4050124 163 #define PDDR 0xA4050126 164 #define PEDR 0xA4050128 165 #define PFDR 0xA405012A 166 #define PGDR 0xA405012C 167 #define PHDR 0xA405012E 168 #define PJDR 0xA4050130 169 #define PKDR 0xA4050132 170 #define PLDR 0xA4050134 171 #define PMDR 0xA4050136 172 #define PNDR 0xA4050138 173 #define PQDR 0xA405013A 174 #define PRDR 0xA405013C 175 #define PSDR 0xA405013E 176 #define PTDR 0xA4050160 177 #define PUDR 0xA4050162 178 #define PVDR 0xA4050164 179 #define PWDR 0xA4050166 180 #define PXDR 0xA4050168 181 #define PYDR 0xA405016A 182 #define PZDR 0xA405016C 183 184 /* UBC */ 185 /* H-UDI */ 186 187 #endif /* _ASM_CPU_SH7723_H_ */ 188
