1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014, Bin Meng <bmeng.cn (at) gmail.com> 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/device-internal.h> 9 #include <pci.h> 10 #include <asm/io.h> 11 #include <asm/irq.h> 12 #include <asm/post.h> 13 #include <asm/arch/device.h> 14 #include <asm/arch/tnc.h> 15 #include <asm/fsp/fsp_support.h> 16 #include <asm/processor.h> 17 18 static int __maybe_unused disable_igd(void) 19 { 20 struct udevice *igd, *sdvo; 21 int ret; 22 23 ret = dm_pci_bus_find_bdf(TNC_IGD, &igd); 24 if (ret) 25 return ret; 26 if (!igd) 27 return 0; 28 29 ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo); 30 if (ret) 31 return ret; 32 if (!sdvo) 33 return 0; 34 35 /* 36 * According to Atom E6xx datasheet, setting VGA Disable (bit17) 37 * of Graphics Controller register (offset 0x50) prevents IGD 38 * (D2:F0) from reporting itself as a VGA display controller 39 * class in the PCI configuration space, and should also prevent 40 * it from responding to VGA legacy memory range and I/O addresses. 41 * 42 * However test result shows that with just VGA Disable bit set and 43 * a PCIe graphics card connected to one of the PCIe controllers on 44 * the E6xx, accessing the VGA legacy space still causes system hang. 45 * After a number of attempts, it turns out besides VGA Disable bit, 46 * the SDVO (D3:F0) device should be disabled to make it work. 47 * 48 * To simplify, use the Function Disable register (offset 0xc4) 49 * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these 50 * two devices will be completely disabled (invisible in the PCI 51 * configuration space) unless a system reset is performed. 52 */ 53 dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE); 54 dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE); 55 56 /* 57 * After setting the function disable bit, IGD and SDVO devices will 58 * disappear in the PCI configuration space. This however creates an 59 * inconsistent state from a driver model PCI controller point of view, 60 * as these two PCI devices are still attached to its parent's child 61 * device list as maintained by the driver model. Some driver model PCI 62 * APIs like dm_pci_find_class(), are referring to the list to speed up 63 * the finding process instead of re-enumerating the whole PCI bus, so 64 * it gets the stale cached data which is wrong. 65 * 66 * Note x86 PCI enueration normally happens twice, in pre-relocation 67 * phase and post-relocation. One option might be to call disable_igd() 68 * in one of the pre-relocation initialization hooks so that it gets 69 * disabled in the first round, and when it comes to the second round 70 * driver model PCI will construct a correct list. Unfortunately this 71 * does not work as Intel FSP is used on this platform to perform low 72 * level initialization, and fsp_init_phase_pci() is called only once 73 * in the post-relocation phase. If we disable IGD and SDVO devices, 74 * fsp_init_phase_pci() simply hangs and never returns. 75 * 76 * So the only option we have is to manually remove these two devices. 77 */ 78 ret = device_remove(igd, DM_REMOVE_NORMAL); 79 if (ret) 80 return ret; 81 ret = device_unbind(igd); 82 if (ret) 83 return ret; 84 ret = device_remove(sdvo, DM_REMOVE_NORMAL); 85 if (ret) 86 return ret; 87 ret = device_unbind(sdvo); 88 if (ret) 89 return ret; 90 91 return 0; 92 } 93 94 int arch_cpu_init(void) 95 { 96 post_code(POST_CPU_INIT); 97 98 return x86_cpu_init_f(); 99 } 100 101 static void tnc_irq_init(void) 102 { 103 struct tnc_rcba *rcba; 104 u32 base; 105 106 pci_read_config32(TNC_LPC, LPC_RCBA, &base); 107 base &= ~MEM_BAR_EN; 108 rcba = (struct tnc_rcba *)base; 109 110 /* Make sure all internal PCI devices are using INTA */ 111 writel(INTA, &rcba->d02ip); 112 writel(INTA, &rcba->d03ip); 113 writel(INTA, &rcba->d27ip); 114 writel(INTA, &rcba->d31ip); 115 writel(INTA, &rcba->d23ip); 116 writel(INTA, &rcba->d24ip); 117 writel(INTA, &rcba->d25ip); 118 writel(INTA, &rcba->d26ip); 119 120 /* 121 * Route TunnelCreek PCI device interrupt pin to PIRQ 122 * 123 * Since PCIe downstream ports received INTx are routed to PIRQ 124 * A/B/C/D directly and not configurable, we have to route PCIe 125 * root ports' INTx to PIRQ A/B/C/D as well. For other devices 126 * on TunneCreek, route them to PIRQ E/F/G/H. 127 */ 128 writew(PIRQE, &rcba->d02ir); 129 writew(PIRQF, &rcba->d03ir); 130 writew(PIRQG, &rcba->d27ir); 131 writew(PIRQH, &rcba->d31ir); 132 writew(PIRQA, &rcba->d23ir); 133 writew(PIRQB, &rcba->d24ir); 134 writew(PIRQC, &rcba->d25ir); 135 writew(PIRQD, &rcba->d26ir); 136 } 137 138 int arch_early_init_r(void) 139 { 140 int ret = 0; 141 142 #ifdef CONFIG_DISABLE_IGD 143 ret = disable_igd(); 144 #endif 145 146 tnc_irq_init(); 147 148 return ret; 149 } 150
