1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * From coreboot soc/intel/broadwell/include/soc/me.h 4 * 5 * Copyright (C) 2014 Google Inc. 6 */ 7 8 #ifndef _asm_arch_me_h 9 #define _asm_arch_me_h 10 11 #include <asm/me_common.h> 12 13 #define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ 14 15 #define ME_HSIO_MESSAGE (7 << 28) 16 #define ME_HSIO_CMD_GETHSIOVER 1 17 #define ME_HSIO_CMD_CLOSE 0 18 19 /* 20 * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according 21 * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature. 22 */ 23 #define PCI_ME_HFS2 0x48 24 /* Infrastructure Progress Values */ 25 #define ME_HFS2_PHASE_ROM 0 26 #define ME_HFS2_PHASE_BUP 1 27 #define ME_HFS2_PHASE_UKERNEL 2 28 #define ME_HFS2_PHASE_POLICY 3 29 #define ME_HFS2_PHASE_MODULE_LOAD 4 30 #define ME_HFS2_PHASE_UNKNOWN 5 31 #define ME_HFS2_PHASE_HOST_COMM 6 32 /* Current State - Based on Infra Progress values. */ 33 /* ROM State */ 34 #define ME_HFS2_STATE_ROM_BEGIN 0 35 #define ME_HFS2_STATE_ROM_DISABLE 6 36 /* BUP State */ 37 #define ME_HFS2_STATE_BUP_INIT 0 38 #define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 39 #define ME_HFS2_STATE_BUP_FLOW_DET 4 40 #define ME_HFS2_STATE_BUP_VSCC_ERR 8 41 #define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa 42 #define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb 43 #define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd 44 #define ME_HFS2_STATE_BUP_M3 0x11 45 #define ME_HFS2_STATE_BUP_M0 0x12 46 #define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 47 #define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 48 #define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 49 #define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 50 #define ME_HFS2_STATE_BUP_T32_MISSING 0x1c 51 #define ME_HFS2_STATE_BUP_WAIT_DID 0x1f 52 #define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 53 #define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 54 #define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 55 #define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 56 #define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 57 #define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 58 #define ME_HFS2_STATE_BUP_M0_CLK 0x26 59 #define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 60 #define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 61 #define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 62 /* Policy Module State */ 63 #define ME_HFS2_STATE_POLICY_ENTRY 0 64 #define ME_HFS2_STATE_POLICY_RCVD_S3 3 65 #define ME_HFS2_STATE_POLICY_RCVD_S4 4 66 #define ME_HFS2_STATE_POLICY_RCVD_S5 5 67 #define ME_HFS2_STATE_POLICY_RCVD_UPD 6 68 #define ME_HFS2_STATE_POLICY_RCVD_PCR 7 69 #define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 70 #define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 71 #define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa 72 #define ME_HFS2_STATE_POLICY_RCVD_DID 0xb 73 #define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc 74 #define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd 75 #define ME_HFS2_STATE_POLICY_FPB_ERR 0xe 76 #define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf 77 #define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 78 /* Current PM Event Values */ 79 #define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 80 #define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 81 #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 82 #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 83 #define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 84 #define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 85 #define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 86 #define ME_HFS2_PMEVENT_S0MO_SXM3 7 87 #define ME_HFS2_PMEVENT_SXM3_S0M0 8 88 #define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 89 #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa 90 #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb 91 #define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc 92 93 struct me_hfs2 { 94 u32 bist_in_progress:1; 95 u32 reserved1:2; 96 u32 invoke_mebx:1; 97 u32 cpu_replaced_sts:1; 98 u32 mbp_rdy:1; 99 u32 mfs_failure:1; 100 u32 warm_reset_request:1; 101 u32 cpu_replaced_valid:1; 102 u32 reserved2:4; 103 u32 mbp_cleared:1; 104 u32 reserved3:2; 105 u32 current_state:8; 106 u32 current_pmevent:4; 107 u32 progress_code:4; 108 } __packed; 109 110 #define PCI_ME_HFS5 0x68 111 112 #define PCI_ME_H_GS2 0x70 113 #define PCI_ME_MBP_GIVE_UP 0x01 114 115 /* ICC Messages */ 116 #define ICC_SET_CLOCK_ENABLES 0x3 117 #define ICC_API_VERSION_LYNXPOINT 0x00030000 118 119 struct icc_header { 120 u32 api_version; 121 u32 icc_command; 122 u32 icc_status; 123 u32 length; 124 u32 reserved; 125 } __packed; 126 127 struct icc_clock_enables_msg { 128 u32 clock_enables; 129 u32 clock_mask; 130 u32 no_response:1; 131 u32 reserved:31; 132 } __packed; 133 134 /* 135 * ME to BIOS Payload Datastructures and definitions. The ordering of the 136 * structures follows the ordering in the ME9 BWG. 137 */ 138 139 #define MBP_APPID_KERNEL 1 140 #define MBP_APPID_INTEL_AT 3 141 #define MBP_APPID_HWA 4 142 #define MBP_APPID_ICC 5 143 #define MBP_APPID_NFC 6 144 /* Kernel items: */ 145 #define MBP_KERNEL_FW_VER_ITEM 1 146 #define MBP_KERNEL_FW_CAP_ITEM 2 147 #define MBP_KERNEL_ROM_BIST_ITEM 3 148 #define MBP_KERNEL_PLAT_KEY_ITEM 4 149 #define MBP_KERNEL_FW_TYPE_ITEM 5 150 #define MBP_KERNEL_MFS_FAILURE_ITEM 6 151 #define MBP_KERNEL_PLAT_TIME_ITEM 7 152 /* Intel AT items: */ 153 #define MBP_INTEL_AT_STATE_ITEM 1 154 /* ICC Items: */ 155 #define MBP_ICC_PROFILE_ITEM 1 156 /* HWA Items: */ 157 #define MBP_HWA_REQUEST_ITEM 1 158 /* NFC Items: */ 159 #define MBP_NFC_SUPPORT_DATA_ITEM 1 160 161 #define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item) 162 #define MBP_IDENT(appid, item) \ 163 MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) 164 165 struct mbp_fw_version_name { 166 u32 major_version:16; 167 u32 minor_version:16; 168 u32 hotfix_version:16; 169 u32 build_version:16; 170 } __packed; 171 172 struct icc_address_mask { 173 u16 icc_start_address; 174 u16 mask; 175 } __packed; 176 177 struct mbp_icc_profile { 178 u8 num_icc_profiles; 179 u8 icc_profile_soft_strap; 180 u8 icc_profile_index; 181 u8 reserved; 182 u32 icc_reg_bundles; 183 struct icc_address_mask icc_address_mask[0]; 184 } __packed; 185 186 struct me_bios_payload { 187 struct mbp_fw_version_name *fw_version_name; 188 struct mbp_mefwcaps *fw_capabilities; 189 struct mbp_rom_bist_data *rom_bist_data; 190 struct mbp_platform_key *platform_key; 191 struct mbp_plat_type *fw_plat_type; 192 struct mbp_icc_profile *icc_profile; 193 struct mbp_at_state *at_state; 194 u32 *mfsintegrity; 195 struct mbp_plat_time *plat_time; 196 struct mbp_nfc_data *nfc_data; 197 }; 198 199 #endif 200
